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參數(shù)資料
| 型號(hào)： | AD9241EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的14位，125 MSPS的單片機(jī)的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 495K |
| 代理商： | AD9241EB |
AD9241
REV. 0
–19–
the A/D may contain serrations to steer currents in predictable
directions where cross-coupling between analog and digital
would otherwise be unavoidable. The AD9241/EB ground lay-
out shown in Figure
52 depicts the serrated type of arrange-
ment. The analog and digital grounds are connected by a jumper
below the A/D.
Analog and Digital Supply Decoupling
The AD9241 features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals.
FREQUENCY – kHz
120
P
100
1000
80
60
40
100
10
1
DVDD
AVDD
Figure 45. PSRR vs. Frequency
Figure 45 shows the power supply rejection ratio vs. frequency
for a 200 mV p-p ripple applied to both AVDD and DVDD.
In general, AVDD, the analog supply, should be decoupled to
AVSS, the analog common, as close to the chip as physically
possible. Figure 46 shows the recommended decoupling for the
analog supplies; 0.1
μ
F ceramic chip capacitors should provide
adequately low impedance over a wide frequency range. Note
that the AVDD and AVSS pins are co-located on the AD9241
to simplify the layout of the decoupling capacitors and provide
the shortest possible PCB trace lengths. The AD9241/EB power
plane layout shown in Figure 53 depicts a typical arrangement
using a multilayer PCB.
0.1μF
AVDD
AVSS
AD9241
0.1μF
AVDD
AVSS
Figure 46. Analog Supply Decoupling
The CML is an internal analog bias point used internally by the
AD9241. This pin must be decoupled with at least a 0.1
μ
F
capacitor as shown in Figure 47. The dc level of CML is ap-
proximately AVDD/2. This voltage should be buffered if it is to
be used for any external biasing.
0.1μF
CML
AD9241
Figure 47. CML Decoupling
The digital activity on the AD9241 chip falls into two general
categories: correction logic and output drivers. The internal
correction logic draws relatively small surges of current, prima-
rily during the clock transitions. The output drivers draw large
current impulses while the output bits are changing. The size
and duration of these currents are a function of the load on the
output bits: large capacitive loads are to be avoided. Note that
the internal correction logic of the AD9241 is referenced DVDD
while the output drivers are referenced to DRVDD.
The decoupling shown in Figure 48 (a 0.1
μ
F ceramic chip
capacitor) is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications in-
volving greater digital loads should consider increasing the digi-
tal decoupling proportionally and/or using external buffers/
latches.
0.1μF
DVDD
DVSS
AD9241
DRVDD
DRVSS
0.1μF
Figure 48. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low-frequency
ripple to negligible levels. Refer to the AD9241/EB schematic
and layouts in
Figures 49–53 for more information regarding the
placement of decoupling capacitors.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9241-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9241 制造商:Analog Devices 功能描述:EVAL BD FOR AD9241 - Bulk |
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| AD9243ASRL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 3Msps 14-bit Parallel 44-Pin MQFP T/R |
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