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| 型號： | AD9245BCPZ-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SGL 65MSPS 32LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 3 |
| 功率耗散（最大）： | 300mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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AD9245
Data Sheet
Rev. E | Page 18 of 32
THEORY OF OPERATION
The AD9245 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The pipelined ADC is divided into three sections
consisting of a 4-bit first stage followed by eight 1.5-bit stages,
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 14-bit result
in the digital correction logic. The pipelined architecture
permits the first stage to operate on a new input sample, while
the remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be
ac-coupled or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment of
the output voltage swing. During power-down, the output
buffers go into a high impedance state.
ANALOG INPUT AND REFERENCE OVERVIEW
The analog input to the AD9245 is a differential switched-
capacitor SHA that has been designed for optimum performance
while processing a differential input signal. The SHA input can
support a wide common-mode range (VCM) and maintain
excellent performance, as shown in Figure 38. An input
common-mode voltage of midsupply minimizes signal-
dependent errors and provides optimum performance.
COMMON-MODE LEVEL (V)
SNR/
SFDR
(
d
Bc)
0.5
1.0
1.5
2.0
2.5
50
100
95
90
85
80
75
70
65
60
55
3.0
0358
3-
039
SFDR (2.5MHz)
SFDR (39MHz)
SNR (2.5MHz)
SNR (39MHz)
Figure 38. AD9245-80 SNR/SFDR vs. Common-Mode Level
Referring to Figure 39, the clock signal alternately switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. In addition, a small shunt capacitor
can be placed across the inputs to provide dynamic charging
currents. This passive network creates a low-pass filter at the
ADC’s input; therefore, the precise values are dependent upon
the application. In IF undersampling applications, any shunt
capacitors should be reduced or removed. In combination with
the driving source impedance, they would limit the input
bandwidth.
03583-
012
H
VIN+
VIN–
CPAR
T
5pF
T
Figure 39. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core. The output common mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as:
REFT = (AVDD + VREF)
REFB = (AVDD VREF)
Span = 2 × (REFT REFB) = 2 × VREF
The previous equations show that the REFT and REFB voltages
are symmetrical about the midsupply voltage, and, by definition,
the input span is twice the value of the VREF voltage.
The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved with the AD9245 set
to the largest input span of 2 V p-p. The relative SNR degradation
is 3 dB when changing from 2 V p-p mode to 1 V p-p mode.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9245BCPZ-652 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter |
| AD9245BCPZ-80 | 功能描述:IC ADC 14BIT 80MSPS 3V 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD9245BCPZ-80 | 制造商:Analog Devices 功能描述:14BIT ADC 3V SMD 9245 LFCSP-32 |
| AD9245BCPZ-802 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter |
| AD9245BCPZRL7-20 | 功能描述:IC ADC 14BIT SGL 20MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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