參數(shù)資料
型號(hào): AD9245BCPZRL7-65
廠商: Analog Devices Inc
文件頁數(shù): 14/32頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SGL 65MSPS 32LFCSP
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 300mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
Data Sheet
AD9245
Rev. E | Page 21 of 32
As detailed in Table 11, the data format can be selected for either
offset binary or twos complement.
TIMING
The AD9245 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9245. These transients can degrade the converter’s dynamic
performance.
The lowest typical conversion rate of the AD9245 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance can degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9245. The input range can be adjusted by varying the
reference voltage applied to the AD9245 using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly. The various reference modes are summarized in Table 10
and described in the following sections.
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common-mode voltage).
INTERNAL REFERENCE CONNECTION
A comparator within the AD9245 detects the potential at the
SENSE pin and configures the reference into one of four
possible states, which are summarized in Table 10. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 45), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in Figure 47, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
R1
R2
VREF
1
5
.
0
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
03583-017
10
F
+
0.1
F
VREF
SENSE
0.5V
AD9245
VIN–
VIN+
REFT
0.1
F
0.1
F
10
F
0.1
F
REFB
SELECT
LOGIC
ADC
CORE
+
Figure 45. Internal Reference Configuration
If the internal reference of the AD9245 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 46 depicts
how the internal reference voltage is affected by loading. A
2 mA load is the maximum recommended load.
LOAD (mA)
ERROR
(
%
)
0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
0358
3-
019
0
–0.25
–0.20
–0.15
–0.10
–0.05
0.5V ERROR (%)
1.0V ERROR (%)
Figure 46. VREF Accuracy vs. Load
Table 10. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
AVDD
N/A
2 × External Reference
Internal Fixed Reference
VREF
0.5
1.0
Programmable Reference
0.2 V to VREF
R1
R2
1
0.5
2 × VREF
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0
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