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參數(shù)資料
| 型號(hào)： | AD9245BCPZRL7-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SGL 80MSPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 414mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
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Data Sheet
AD9245
Rev. E | Page 19 of 32
The SHA can be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as
2
VREF
VCMMIN =
(
)
2
VREF
AVDD
VCMMAX
+
=
The minimum common-mode input level allows the AD9245 to
accommodate ground referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source can be applied to VIN+ or VIN–.
In this configuration, one input accepts the signal, while the
opposite input is set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal can be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9245 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
can degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies.
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9245 in a differential input configuration. For
baseband applications, the AD8351 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8351 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
03583
-013
AD9245
VIN+
VIN–
AGND
AVDD
2V p-p
33
20pF
AD8351
1k
0.1F
1.2k
25
0.1mF
25
50
Figure 40. Differential Input Configuration Using the AD8351
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9245. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The value of the shunt capacitor is dependent on
the input frequency and source impedance and should be
reduced or removed. An example is shown in Figure 41.
03583-
014
AD9245
VIN+
VIN–
AVDD
AGND
33
33
20pF
49.9
1k
1k
0.1
F
2V p-p
Figure 41. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing (see Figure 13). However, if
the source impedances on each input are matched, there should
be little effect on SNR performance. Figure 42 details a typical
single-ended input configuration.
03583-
015
AD9245
VIN+
VIN–
AVDD
AGND
2V p-p
33
33
20pF
49.9
1k
1k
0.33
F
10
F
0.1
F
1k
1k
+
Figure 42. Single-Ended Input Configuration
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result can be sensitive
to clock duty cycle. Commonly a 5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9245-80 and AD9245-65 contain a clock duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing an
internal clock signal with a nominal 50% duty cycle. This allows a
wide range of clock input duty cycles without affecting the
performance of the AD9245. As shown in Figure 21, noise and
distortion performance is nearly flat for a 30% to 70% duty cycle
with the DCS on.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9245BCPZRL7-802 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter |
| AD9245BPCZ-80 | 制造商:Analog Devices 功能描述:14BIT 80MSPS - Bulk 制造商:Analog Devices 功能描述:Analog Devices AD9245BPCZ-80 Data Conversions |
| AD9245XCPZ-20 | 制造商:Analog Devices 功能描述:40 MSPS DUAL A/D CONVERTER - Bulk |
| AD9246 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter |
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