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參數(shù)資料
| 型號： | AD9251BCPZRL7-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 65MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 146.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9251
Rev. A | Page 31 of 36
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table (see Table 16) has
eight bit locations. The memory map is roughly divided into
four sections: the chip configuration registers (Address 0x00 to
Address 0x02); the device index and transfer registers (Address
0x05 and Address 0xFF); the program registers, including setup,
control, and test (Address 0x08 to Address 0x2E); and the
digital feature control registers (Address 0x100 and Address
0x101).
Table 16 documents the default hexadecimal value for each
hexadecimal address shown. The column with the heading Bit 7
(MSB) is the start of the default hexadecimal value given. For
example, Address 0x05, the Channel Index register, has a
hexadecimal default value of 0x03. This means that in Address
0x05 Bit[7:2] = 0, and the remaining Bits[1:0] = 1. This setting
is the default channel index setting. The default value results in
both ADC channels receiving the next write command. For
more information on this function and others, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI. This
document details the functions controlled by Register 0x00 to
register 0xFF. The remaining registers, Register 0x100 and
Register 0x101, are documented in the Memory Map Register
Descriptions section following Table 16.
OPEN LOCATIONS
All address and bit locations that are not included in the SPI
map are not currently supported for this device. Unused bits of
a valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x05). If the entire address location
is open, it is omitted from the SPI map (for example, Address 0x13)
and should not be written.
DEFAULT VALUES
After the AD9251 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (see Table 16).
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simulta-
neously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and then the bit autoclears.
Channel-Specific Registers
Some channel setup functions can be programmed differently
for each channel. In these cases, channel address locations are
internally duplicated for each channel. These registers and bits
are designated in the memory map register table as local. These
local registers and bits can be accessed by setting the appropriate
Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05.
If both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, set only Channel A or Channel B
to read one of the two registers. If both bits are set during an
SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in the memory map
register table affect the entire part or the channel features for
which independent settings are not allowed between channels.
The settings in Register 0x05 do not affect the global registers
and bits.
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