參數(shù)資料
型號(hào): AD9281ARS
廠商: Analog Devices Inc
文件頁(yè)數(shù): 3/15頁(yè)
文件大小: 0K
描述: IC ADC 8BIT DUAL CMOS 28-SSOP
標(biāo)準(zhǔn)包裝: 47
位數(shù): 8
采樣率(每秒): 28M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 260mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,單極
AD9281
–11–
QREFT
QREFB
IREFT
0.1 F10 F
0.1 F
AD9281
REFSENSE
AVSS
1V
0.1 F
10 F
IREFB
VREF
0.1 F
10k
ADC
CORE
INTERNAL
CONTROL
LOGIC
0.1 F
1.0 F
Figure 26. Reference Buffer Equivalent Circuit and
External Decoupling Recommendation
For best results in both noise suppression and robustness
against crosstalk, the 4-capacitor buffer decoupling arrangement
shown in Figure 26 is recommended. This decoupling should
–3
–0.5
THD
dB
–13
–23
–33
–43
–53
–63
–73
0
0.5
1
1.5
CML – V
2V
1V
a. Differential Input, 3 V Supplies
–35
–0.5
THD
dB
–40
–45
–50
–55
–60
–65
–70
0
0.5
1
1.5
CML – V
2
2.5
1V
2V
b. Differential Input, 5 V Supplies
Figure 27. THD vs. CML Input Span and Power Supply (Analog Input = 1 MHz)
–15
–0.5
THD
dB
–25
–35
–45
–55
–65
0
0.5
1
1.5
CML – V
2V
1V
c. Single-Ended Input, 3 V Supplies
–15
–0.5
THD
dB
–25
–35
–45
–55
–65
0
0.5
1
1.5
CML – V
2V
1V
2
2.5
d. Single-Ended Input, 5 V Supplies
feature chip capacitors located close to the converter IC. The
capacitors are connected to either IREFT/IREFB or QREFT/
QREFB. A connection to both sides is not required.
COMMON-MODE PERFORMANCE
Attention to the common-mode point of the analog input volt-
age can improve the performance of the AD9281. Figure 27
illustrates THD as a function of common-mode voltage (center
point of the analog input span) and power supply.
Inspection of the curves will yield the following conclusions:
1. An AD9281 running with AVDD = 5 V is the easiest to
drive.
2. Differential inputs are the most insensitive to common-mode
voltage.
3. An AD9281 powered by AVDD = 3 V and a single ended
input, should have a 1 V span with a common-mode voltage
of 0.75 V.
REV. F
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