參數(shù)資料
型號: AD9281ARSZRL
廠商: Analog Devices Inc
文件頁數(shù): 1/15頁
文件大?。?/td> 0K
描述: IC ADC 8BIT DUAL CMOS 28SSOP
產(chǎn)品培訓模塊: ADC Applications
ADC Architectures
ADC DC/AC Performance
標準包裝: 1,500
位數(shù): 8
采樣率(每秒): 28M
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 2
功率耗散(最大): 260mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,雙極;2 個差分,雙極
AD9281
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax:
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Dual Channel 8-Bit
Resolution CMOS ADC
FEATURES
Complete Dual Matching ADC
Low Power Dissipation: 225 mW (+3 V Supply)
Single Supply: 2.7 V to 5.5 V
Differential Nonlinearity Error: 0.1 LSB
On-Chip Analog Input Buffers
On-Chip Reference
Signal-to-Noise Ratio: 49.2 dB
Over Seven Effective Bits
Spurious-Free Dynamic Range: –65 dB
No Missing Codes Guaranteed
28-Lead SSOP
FUNCTIONAL BLOCK DIAGRAM
1V
REFERENCE
BUFFER
QREFB
IREFB
QREFT
IREFT
VREF
REFSENSE
IINA
IINB
"I" ADC
QINB
QINA
"Q" ADC
Q
REGISTER
I
REGISTER
THREE-
STATE
OUTPUT
BUFFER
AVDD AVSS
CLOCK
DVDD DVSS
SLEEP
SELECT
DATA
8 BITS
CHIP
SELECT
AD9281
ASYNCHRONOUS
MULTIPLEXER
PRODUCT DESCRIPTION
The AD9281 is a complete dual channel, 28 MSPS, 8-bit
CMOS ADC. The AD9281 is optimized specifically for applica-
tions where close matching between two ADCs is required (e.g.,
I/Q channels in communications applications). The 28 MHz
sampling rate and wide input bandwidth will cover both narrow-
band and spread-spectrum channels. The AD9281 integrates
two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal
voltage reference and multiplexed digital output buffers.
Each ADC incorporates a simultaneous sampling sample-and-
hold amplifier at its input. The analog inputs are buffered; no
external input buffer op amp will be required in most applica-
tions. The ADCs are implemented using a multistage pipeline
architecture that offers accurate performance and guarantees no
missing codes. The outputs of the ADCs are ported to a multi-
plexed digital output buffer.
The AD9281 is manufactured on an advanced low cost CMOS
process, operates from a single supply from 2.7 V to 5.5 V, and
consumes 225 mW of power (on 3 V supply). The AD9281
input structure accepts either single-ended or differential signals,
providing excellent dynamic performance up to and beyond
14 MHz Nyquist input frequencies.
PRODUCT HIGHLIGHTS
1. Dual 8-Bit, 28 MSPS ADC
A pair of high performance 28 MSPS ADCs that are opti-
mized for spurious free dynamic performance are provided for
encoding of I and Q or diversity channel information.
2. Low Power
Complete CMOS Dual ADC function consumes a low
225 mW on a single supply (on 3 V supply). The AD9281
operates on supply voltages from 2.7 V to 5.5 V.
3. On-Chip Voltage Reference
The AD9281 includes an on-chip compensated bandgap
voltage reference pin programmable for 1 V or 2 V.
4. On-chip analog input buffers eliminate the need for external
op amps in most applications.
5. Single 8-Bit Digital Output Bus
The AD9281 ADC outputs are interleaved onto a single
output bus saving board space and digital pin count.
6. Small Package
The AD9281 offers the complete integrated function in a
compact 28-lead SSOP package.
7. Product Family
The AD9281 dual ADC is pin compatible with a dual 10-bit
ADC (AD9201).
REV. F
1999-2011 Analog Devices, Inc. All rights reserved.
781/461-3113
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