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參數(shù)資料
| 型號(hào)： | AD9284BCPZ-250 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 250MSPS 1.8V 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 250M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 330mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，雙極 |
| 配用： | AD9284-250EBZ-ND - BOARD EVAL FOR AD9284 |
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Data Sheet
AD9284
Rev. A | Page 15 of 24
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9284 includes a built-in self-test feature that is designed
to enable verification of the integrity of each channel, as well as
facilitate board level debugging. A built-in self-test (BIST) feature
that verifies the integrity of the digital datapath of the AD9284
is included. Various output test options are also provided to
place predictable values on the outputs of the AD9284.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9284 signal path. Perform the BIST test after a reset to ensure
that the part is in a known state. During BIST, data from an
internal pseudorandom noise (PN) source is driven through
the digital datapath of both channels, starting at the ADC block
output. At the datapath output, CRC logic calculates a signature
from the data. The BIST sequence runs for 512 cycles and then
stops. When the test is completed, the BIST compares the signature
results with a predetermined value. If the signatures match, the
BIST sets Bit 0 of Register 0x0E, signifying that the test passed.
If the BIST test fails, Bit 0 of Register 0x0E is cleared. The outputs
are connected during this test, so the PN sequence can be observed
as it runs.
Writing a value of 0x05 to Register 0x0E runs the BIST. This
enables Bit 0 (BIST enable) of Register 0x0E and resets the PN
sequence generator, Bit 2 (BIST init) of Register 0x0E. At the
completion of the BIST, Bit 0 of Register 0x0E is automatically
cleared. The PN sequence can be continued from its last value
by writing a 0 to Bit 2 of Register 0x0E. However, if the PN
sequence is not reset, the signature calculation does not equal
the predetermined value at the end of the test. At that point, the
user must rely on verifying the output data.
OUTPUT TEST MODES
The output test options are described in Table 12 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back-end blocks, and the
test pattern is run through the output formatting block. Some
test patterns are subject to output formatting, and some are not.
The PN generators from the PN sequence tests can be reset by
setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed
with or without an analog signal (if present, the analog signal
is ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
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