參數(shù)資料
型號: AD9286BCPZRL7-500
廠商: Analog Devices Inc
文件頁數(shù): 17/28頁
文件大?。?/td> 0K
描述: IC ADC 8BIT SPI/SRL 500M 48LFCSP
標準包裝: 750
位數(shù): 8
采樣率(每秒): 500M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 330mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個差分,雙極
AD9286
Data Sheet
Rev. B | Page 24 of 28
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x0F
ADC input
(global/local)
Open
Analog
disconnect
(local)
Common-
mode
input
enable
(global)
Open
0x00
0x10
Offset (local)
Open
Offset adjust (twos complement format)
0111: +7
0110: +6
0001: +1
0000: 0
1111: 1
1001: 7
1000: 8
0x00
Device
offset trim
0x14
Output
mode (local)
Open
Output
enable
Open
Output
invert
Data format select
00: offset binary
01: twos complement
10: Gray code
11: reserved
0x00
Configures
the outputs
and the
format of
the data
0x16
Output
phase
(global)
DCO invert
Open
0x00
0x18
Voltage
reference
(global)
Open
Voltage reference and input full-scale adjustment (see Table 14)
0x00
Selects/
adjusts VREF
0x24
MISR LSB
(local)
LSBs of multiple input shift register (MISR)
0x00
MISR least
significant
byte; read
only
0x25
MISR MSB
(local)
MSBs of multiple input shift register (MISR)
0x00
MISR most
significant
byte; read
only
0x37
Timing
adjust (local)
Open
Fine timing skew
0000: 0.0 ps
0001: 0.075 ps
1111: 1.125 ps
0x00
Determines
the clock
delay that is
introduced
into the
sampling
path
0x38
Open
Coarse timing skew
0000: 0.0 ps
0001: 1.2 ps
1111: 18 ps
0x00
Determines
the clock
delay that is
introduced
into the
sampling
path
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