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| 型號(hào)： | AD9433BSQ-105 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52 |
| 封裝： | POWER, PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大小： | 1001K |
| 代理商： | AD9433BSQ-105 |
REV. 0
–2–
AD9433–SPECIFICATIONS
DC SPECIFICATIONS
(V
DD
= 3.3 V, V
CC
= 5 V; internal reference; differential encode input, unless otherwise noted.)
Test
Level
AD9433BSQ-105
Min
Typ
AD9433BSQ-125
Min
Typ
Parameter
Temp
Max
Max
Unit
RESOLUTION
12
12
Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Full
Full
25 C
25 C
Full
25 C
Full
VI
VI
I
I
VI
I
VI
Guaranteed
0
1
0.25
Guaranteed
0
1
0.3
–5
–7
–0.75
–1
–1.0
–1.3
+5
+3
+0.75
+1
+1.0
+1.3
–5
–7
–0.75
–1
–1.0
–1.3
+5
+3
+0.75
+1
+1.0
+1.3
mV
% FS
LSB
LSB
LSB
LSB
Integral Nonlinearity (INL)
2
0.5
0.5
THERMAL DRIFT
Offset Error
Gain Error
1
Reference
Full
Full
Full
V
V
V
–50
–125
±
80
–50
–125
±
80
ppm/ C
ppm/ C
ppm/ C
REFERENCE
Internal Reference Volatge (VREFOUT)
Output Current (VREFOUT)
Input Current (VREFIN)
Full
Full
Full
I
V
IV
2.4
2.5
100
2.6
2.4
2.5
100
2.6
V
μ
A
μ
A
50
50
ANALOG INPUTS
Differential Input Voltage Range
(
AIN
, AIN)
Common-Mode Voltage
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
Full
V
2.0
2.0
V
Full
Full
Full
Full
V
VI
V
V
4.0
3
4
750
4.0
3
4
750
V
k
pF
MHz
2
4
2
4
POWER SUPPLY
V
CC
V
DD
Power Dissipation
3
Power Supply Rejection Ratio (PSRR)
IV
CC2
IV
DD2
ENCODE INPUTS
Internal Common-Mode Bias
Differential Input (ENC –
ENC
)
Input Voltage Range
Input Common-Mode Range
Input Resistance
Input Capacitance
Full
Full
Full
25 C
Full
Full
IV
IV
VI
I
VI
VI
4.75
2.7
5.0
5.25
3.3
1425
4.75
2.7
5.0
5.25
3.3
1500
V
V
mW
mV/V
mA
mA
1275
3
255
12.5
1350
3
270
16
285
14
300
18
Full
Full
Full
Full
Full
25 C
V
V
IV
IV
VI
V
3.75
500
3.75
500
V
mV
–0.5
2.0
V
CC
+ 0.05
4.25
–0.5
2.0
V
CC
+ 0.05 V
4.25
V
k
pF
6
3
6
3
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input High Current (VIN = 5 V)
Input Low Current (VIN = 0 V)
Full
Full
Full
Full
I
I
V
V
2.0
2.0
V
V
μ
A
μ
A
0.8
0.8
50
50
50
50
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Output Coding
Full
Full
VI
VI
V
DD
– 0.05
V
DD
– 0.05
V
V
0.05
0.05
Two’s Complement or Offset Binary
NOTES
1
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).
2
SFDR disabled (SFDR = GND) for DNL and INL specifications.
3
Power dissipation measured with rated encode and a dc analog input (Outputs Static, I
VDD
= 0). I
VCC
and I
VDD
measured with 10.3 MHz analog input @ –0.5 dBFS.
Specifications subject to change without notice.
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