- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373963 > AD9480-LVDS-PCB3 (Analog Devices, Inc.) 8-Bit, 250 MSPS 3.3 V A/D Converter PDF資料下載
參數(shù)資料
| 型號： | AD9480-LVDS-PCB3 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 250 MSPS 3.3 V A/D Converter |
| 中文描述： | 8位，250MSPS的3V A/D轉換器 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 1146K |
| 代理商： | AD9480-LVDS-PCB3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD9480
APPLICATION NOTES
The AD9480 uses a 1.5 bit per stage architecture. The analog
inputs drive an integrated high bandwidth track-and-hold
circuit that samples the signal prior to quantization by the 8-bit
core. For ease of use, the part includes an on-board reference
and input logic that accepts TTL, CMOS, or LVPECL levels. The
digital output logic levels are LVDS (ANSI 644 compatible).
Rev. 0 | Page 12 of 28
CLOCKING THE AD9480
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track-and-
hold circuit is essentially a mixer, and any noise, distortion, or
timing jitter on the clock is combined with the desired signal at
the A/D output. Considerable care has been taken in the design
of the CLOCK input of the AD9480, and the user is advised to
give commensurate thought to the clock source.
The AD9480 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of CLOCK and optimizes
timing internally for sample rates between 100 MSPS and
250 MSPS. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter on the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates less than 70 MHz
nominally. The loop has a time constant associated with it that
needs to be considered in applications where the clock rate can
change dynamically, requiring a wait time of 5 μs after a
dynamic clock frequency increase before valid data is available.
The clock duty cycle stabilizer can be disabled at Pin 28 (S1).
The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
MC100LVEL16 performs well in the circuit to drive the clock
inputs (ac coupling is optional). If the clock buffer is greater
than 2 inches from the ADC, a standard LVPECL termination
may be required instead of the simple pull-down termination
shown in Figure 10.
0
AD9480
CLK+
0.1
μ
F
0.1
μ
F
510k
510k
PECL
GATE
CLK–
Figure 10. Clocking the AD9480
ANALOG INPUTS
The analog input to the AD9480 is a differential buffer. For best
dynamic performance, impedances at VIN+ and VIN
should
match. Optimal performance is obtained when the analog
inputs are driven differentially. SNR and SINAD performance
can degrade if the analog input is driven with a single-ended
signal. The analog inputs self-bias to approximately 1.9 V; this
common-mode voltage can be externally overdriven by
approximately ±300 mV if required.
A wideband transformer, such as the Minicircuits ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Note that the
filter and center-tap capacitor on the secondary side is optional
and dependent on application requirements. An RC filter at the
secondary side helps reduce any wideband noise getting aliased
by the ADC.
0
AD9480
VIN+
AVDD
(R, C OPTIONAL)
AGND
0.1
μ
F
10pF
33
33
49.9
VIN–
Figure 11. Driving the ADC with an RF Transformer
For dc-coupled applications, the AD8138 or AD8351 can
serve as a convenient ADC driver, depending on requirements.
Figure 12 shows an example with the AD8138. The AD9480
PCB has an optional AD8351 on board, as shown in Figure 41
and Figure 42. The AD8351 typically yields better performance
for frequencies greater than 30 MHz to 40 MHz.
0
AD9480
AD8138
VIN+
AVDD
AGND
0.1
μ
F
20pF
33
33
VIN–
49.9
2k
1.3k
499
499
523
499
Figure 12. Driving the ADC with the AD8138
Table 8. S1 Voltage Levels
S1 Voltage
0.9*AVDD
> AVDD
2/3 AVDD ± (0.1*AVDD)
1/3 AVDD ± (0.1*AVDD)
AGND
>(0.1*AVDD)
Data Format
Offset binary
Offset binary
Twos complement
Twos complement
Duty Cycle Stabilizer
Disabled
Enabled
Enabled
Disabled
相關PDF資料 |
PDF描述 |
|---|---|
| AD9480ASUZ-2501 | 8-Bit, 250 MSPS 3.3 V A/D Converter |
| AD9480BSUZ-2501 | 8-Bit, 250 MSPS 3.3 V A/D Converter |
| AD9483KS-100 | Triple 8-Bit, 140 MSPS A/D Converter |
| AD9483KS-140 | Triple 8-Bit, 140 MSPS A/D Converter |
| AD9483 | Triple 8-Bit, 140 MSPS A/D Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9480XSU-250 | 制造商:Analog Devices 功能描述:8-BIT, 250 MSPS, 3.3 V A/D CONVERTER - Bulk |
| AD9481 | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Bit, 250 MSPS 3.3 V A/D Converter |
| AD9481BSUZ-250 | 功能描述:IC ADC 8BIT 250MSPS 3.3V 44-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9481-PCB | 制造商:Analog Devices 功能描述:EVAL KIT FOR 8BIT, 250 MSPS 3.3V A/D CNVRTR - Bulk |
| AD9481-PCBZ | 功能描述:BOARD EVAL 8BIT 250MSPS 44-TQFP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。