參數(shù)資料
型號(hào)： AD9500
廠商： Analog Devices, Inc.
英文描述： Digitally Programmable Delay Generator
中文描述： 數(shù)字可編程延時(shí)發(fā)生器
文件頁(yè)數(shù)： 1/11頁(yè)
文件大小： 131K
代理商： AD9500
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Digitally Programmable
Delay Generator
AD9500
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD9500 is a digitally programmable delay generator, which
provides programmed delays, selected through an 8-bit digital
code, in resolutions as small as 10 ps. The AD9500 is con-
structed in a high performance bipolar process, designed to
provide high speed operation for both digital and analog circuits.
The AD9500 employs differential TRIGGER and RESET
inputs which are designed primarily for ECL signal levels but
function with analog and TTL input levels. An onboard ECL
reference midpoint allows both of the inputs to be driven by
either single ended or differential ECL circuits. The AD9500
output is a complementary ECL stage, which also provides a
Q
R
parallel output circuit to facilitate reset timing implementations.
The digital control data is passed to the AD9500 through a
transparent latch controlled by the LATCH ENABLE signal. In
the transparent mode, the internal DAC of the AD9500 will
attempt to follow changes at the inputs. The LATCH ENABLE
is otherwise used to strobe the digital data into the AD9500
latches.
The AD9500 is available as an industrial temperature range
device, –25
°
C to +85
°
C, and as an extended temperature range
device, –55
°
C to +125
°
C. Both grades are packaged in a 24-lead
cerdip (0.3" package width), as well as 28-leaded and leadless
surface mount packages. The AD9500 is available in versions
compliant with MIL-STD-883. Refer to the Analog Devices
Military Products Databook or current AD9500/883B data
sheet for detailed specifications.
FEATURES
10 ps Delay Resolution
2.5 ns to 10
m
s Full-Scale Range
Fully Differential Inputs
Separate Trigger and Reset Inputs
Low Power Dissipation—310 mW
MIL-STD-883 Compliant Versions Available
APPLICATIONS
ATE
Pulse Deskewing
Arbitrary Waveform Generators
High Stability Timing Source
Multiple Phase Clock Generators
DIFFERENTIAL
ANALOG
INPUT
STAGE
ECL
VOLTAGE
REFERENCE
REFERENCE
CURRENT
TIMING
CONTROL
CIRCUIT
OFFSET
ADJUST
LATCH
ENABLE
GROUND
ECL COMMON
Q
TRIGGER
RESET
ECL
REF
D
0
(LSB)
C
S
+V
S
TRIGGER
RESET
Q
R
Q
INTERNAL DAC
TTL LATCHES
D
7
(MSB)
D
1
AD9500
C
EXT
R
SET
R
S
–V
S
–V
S
D
2
D
3
D
4
D
5
D
6
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TOP VIEW
(Not to Scale)
D
4
D
5
D
7
(MSB)
ECL
REF
OFFSET ADJUST
C
S
+V
S
D
3
D
2
D
1
D
0
(LSB)
LATCH ENABLE
GROUND
R
S
–V
S
ECL COMMON
Q
TRIGGER
RESET
TRIGGER
RESET
Q
R
Q
AD9500
D
6
TOP VIEW
(Not to Scale)
4
3
2
1
28
27
26
12
T
13
R
14
R
15
N
16
Q
17
Q
18
Q
R
25
24
23
22
21
20
19
5
6
7
8
9
10
11
LATCH ENABLE
GROUND
ECL COMMON
OFFSET ADJUST
TRIGGER
D
7
(MSB)
ECL
REF
C
S
+V
S
D
6
N
NC
NC
AD9500
D
5
D
4
D
3
D
2
D
1
D
0
(LSB)
R
S
–V
S
NC = NO CONNECT
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
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