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參數(shù)資料
| 型號： | AD9501 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | 數(shù)字可編程延時發(fā)生器 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 180K |
| 代理商： | AD9501 |
AD9501
REV. A
–10–
Figure 8. Digital Delay Detector
Figure 7. Programmable Pulse Delay Generator
AD9501 #1 should be programmed so its delay is greater than
the zero-set programmed delay of AD9501 #2. T o accomplish
this, continue to apply clock pulses and increment the digital
data into AD9501 #1 until the output of the successive approxi-
mation register (SAR) is 02H (00000010) or greater. At this
point, the delay through AD9501 #1 is slightly longer than the
delay through AD9501 #2, making it possible to use the SAR
output as the zero reference point for measuring the unknown
delay when it is reinserted into the circuit.
T his calibration procedure compensates for the setup time of
the flip-flop, stray circuit delays and other nonideal characteristics
which are an inherent part of any circuit.
Eight cycles of the clock input are required to determine the
value of the unknown delay.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9501JN | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digitally Programmable Delay Generator |
| AD9501JP | 制造商:Analog Devices 功能描述: |
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| AD9501SE | 制造商:Analog Devices 功能描述: |
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