參數(shù)資料
型號: AD9501JN
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調(diào)理
英文描述: Digitally Programmable Delay Generator
中文描述: SPECIALTY ANALOG CIRCUIT, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 2/12頁
文件大?。?/td> 180K
代理商: AD9501JN
REV. A
–2–
AD9501–SPECIFICATIONS
ABSOLUT E MAX IMUM RAT INGS
1
Positive Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Digital Input Voltage Range . . . . . . . . . . . . . . . –0.5 V to +V
S
T rigger/Reset Input Volt. Range . . . . . . . . . . . . –0.5 V to +V
S
Minimum R
SET
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Digital Output Current (Sourcing) . . . . . . . . . . . . . . . 10 mA
Digital Output Current (Sinking) . . . . . . . . . . . . . . . . 50 mA
Operating T emperature Range
AD9501JN/JP/JQ . . . . . . . . . . . . . . . . . . . . . . 0
°
C to +70
°
C
AD9501SQ . . . . . . . . . . . . . . . . . . . . . . . –55
°
C to +125
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Junction T emperature
2
. . . . . . . . . . . . . . . . . . . . . . . +175
°
C
Lead Soldering T emperature (10 sec) . . . . . . . . . . . . +300
°
C
ELECTRICAL CHARACTERISTICS
[+V
S
= +5 V; C
EXT
= Open; R
SET
= 3090
(Full-Scale Range =100 ns); Pin 8 grounded; and
device output connected to Pin 4 RESET input unless otherwse noted]
0
8
C to +70
8
C
AD9501JN/JP/JQ
Min
T yp
–55
8
C to +125
8
C
AD9501SQ
Min
T yp
T est
Level
Parameter
T emp
Max
Max
Units
RESOLUT ION
8
8
Bits
ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Monotonicity
+25
°
C
+25
°
C
+25
°
C
I
I
I
0.5
1
0.5
1
LSB
LSB
Guaranteed
Guaranteed
DIGIT AL INPUT S
Latch Input “1” Voltage
Latch Input “0” Voltage
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Digital Input Capacitance
Data Setup T ime (t
S
)
3
Data Hold T ime (t
H
)
4
Latch Pulse Width (t
L
)
Reset/T rigger Pulse Width (t
R
, t
T
)
Full
Full
Full
Full
Full
Full
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
VI
VI
VI
VI
VI
VI
IV
V
V
V
V
2.0
2.3
V
V
V
V
μ
A
μ
A
pF
ns
ns
ns
ns
0.8
0.8
2.0
2.0
0.8
60
3
5.5
0.8
60
3
5.5
2.5
2.5
3.5
2
2.5
2.5
3.5
2
DYNAMIC PERFORMANCE
Maximum T rigger Rate
5
Minimum Propagation Delay (t
PD
)
6
Propagation Delay T empco
7
Full-Scale Range T empco
Delay Uncertainty
Reset Propagation Delay (t
RD
)
8
Reset-to-T rigger Holdoff (t
T HO
)
9
T rigger-to-Reset Holdoff (t
RHO
)
10
Minimum Output Pulse Width
11
Output Rise T ime
12
Output Fall T ime
12
DAC Settling T ime (t
LD
)
13
Linear Ramp Settling T ime (t
LRS
)
14
+25
°
C
+25
°
C
Full
Full
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
IV
I
V
V
V
I
V
V
V
I
I
V
V
18
22
25
25
36
53
14.5
4.5
19
7.5
2.3
1.0
30
20
18
22
25
25
36
53
14.5
4.5
19
7.5
2.3
1.0
30
20
MHz
ns
ps/
°
C
ps/
°
C
ps
ns
ns
ns
ns
ns
ns
ns
ns
30
30
17.5
17.5
3.5
2.0
3.5
2.0
DIGIT AL OUT PUT
Logic “1” Voltage (Source 1 mA)
Logic “0” Voltage (Sink 4 mA)
Full
Full
VI
VI
2.4
2.4
V
V
0.24
0.4
0.24
0.5
POWER SUPPLY
15
Positive Supply Current (+5.0 V)
Power Dissipation
Power Supply Rejection Ratio
16
Full-Scale Range Sensitivity
Minimum Prop Delay Sensitivity
Full
Full
VI
VI
69.5
83
415
69.5
83
415
mA
mW
+25
°
C
+25
°
C
I
I
0.7
0.45
2.0
1.7
0.7
0.45
2.0
1.7
ns/V
ns/V
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