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參數(shù)資料
| 型號： | AD9513BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIST 3OUT PLL 32LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 扇出緩沖器（分配），除法器 |
| PLL： | 無 |
| 輸入： | 時鐘 |
| 輸出： | CMOS，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 800MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9513/PCBZ-ND - BOARD EVAL FOR AD9513 |
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AD9513
Rev. 0 | Page 17 of 28
FUNCTIONAL DESCRIPTION
OVERALL
The AD9513 provides for the distribution of its input clock on
up to three outputs. Each output can be set to either LVDS or
CMOS logic levels. Each output has its own divider that can be
set for a divide ratio selected from a list of integer values from
1 (bypassed) to 32.
OUT2 includes an analog delay block that can be set to add an
additional delay of 1.8 ns, 6.0 ns, or 11.6 ns full scale, each with
16 levels of fine adjustment.
CLK, CLKB—DIFFERENTIAL CLOCK INPUT
The CLK and CLKB pins are differential clock input pins.
This input works up to 1600 MHz. The jitter performance is
degraded by a slew rate below 1 V/ns. The input level should be
between approximately 150 mV p-p to no more than 2 V p-p.
Anything greater can result in turning on the protection diodes
on the input pins.
See Figure 18 for the CLK equivalent input circuit. This input
is fully differential and self-biased. The signal should be ac-
coupled using capacitors. If a single-ended input must be used,
this can be accommodated by ac coupling to one side of the
differential input only. The other side of the input should be
bypassed to a quiet ac ground by a capacitor.
2.5k
5k
2.5k
CLKB
CLK
VS
CLOCK INPUT
STAGE
055
95-
021
Figure 18. Clock Input Equivalent Circuit
SYNCHRONIZATION
Power-On SYNC
A power-on sync (POS) is issued when the VS power supply is
turned on to ensure that the outputs start in synchronization.
The power-on sync works only if the VS power supply transi-
tions the region from 2.2 V to 3.1 V within 35 ms. The POS can
occur up to 65 ms after VS crosses 2.2 V. Only outputs which are
not divide = 1 are synchronized.
CLK
OUT
0V
3.3V
2.2V
3.1V
VS
CLOCK FREQUENCY
IS EXAMPLE ONLY
DIVIDE = 2
PHASE = 0
< 65ms
INTERNAL SYNC NODE
35ms
MAX
0559
5-
094
Figure 19. Power-On Sync Timing
SYNCB
If the setup configuration of the AD9513 is changed during
operation, the outputs can become unsynchronized. The
outputs can be resynchronized to each other at any time.
Synchronization occurs when the SYNCB pin is pulled low and
released. The clock outputs (except where divide = 1) are forced
into a fixed state (determined by the divide and phase settings)
and held there in a static condition, until the SYNCB pin is
returned to high. Upon release of the SYNCB pin, after four
cycles of the clock signal at CLK, all outputs continue clocking
in synchronicity (except where divide = 1).
When divide = 1 for an output, that output is not affected by
SYNCB.
CLK
SYNCB
OUT
3 CLK CYCLES
4 CLK CYCLES
EXAMPLE: DIVIDE ≥ 8
PHASE = 0
EXAMPLE DIVIDE
RATIO PHASE = 0
05
595
-0
93
Figure 20. SYNCB Timing with Clock Present
4 CLK CYCLES
CLK
OUT
SYNCB
DEPENDS ON PREVIOUS STATE AND DIVIDE RATIO
§§
§
DEPENDS ON PREVIOUS STATE
EXAMPLE DIVIDE
RATIO PHASE = 0
MIN 5ns
05595-
092
Figure 21. SYNCB Timing with No Clock Present
The outputs of the AD9513 can be synchronized by using the
SYNCB pin. Synchronization aligns the phases of the clock
outputs, respecting any phase offset that has been set on an
output’s divider.
SYNCB
05595
-022
Figure 22. SYNCB Equivalent Input Circuit
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9514 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514/PCB | 制造商:Analog Devices 功能描述:CLOCK DISTRIBUTION - Bulk |
| AD9514/PCBZ | 功能描述:BOARD EVAL CLOCK 3CH AD9514 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9514BCPZ | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9514BCPZ-REEL7 | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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