參數(shù)資料
型號(hào)： AD9516-4BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 74/80頁
文件大?。?/td> 0K
描述： IC CLOCK GEN 1.6GHZ VCO 64-LFCSP
設(shè)計(jì)資源： AD9516 Eval Brd Schematic
AD9516 Gerber Files
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： 時(shí)鐘
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:14
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.8GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
產(chǎn)品目錄頁面： 776 (CN2011-ZH PDF)
配用： AD9516-4/PCBZ-ND - BOARD EVAL FOR AD9516-4 1.8GHZ
AD9516-4
Data Sheet
Rev. C | Page 76 of 80
Table 60. VCO Divider and CLK Input
Reg.
Addr
(Hex)
Bits
Name
Description
0x1E0
[2:0]
VCO divider
2
1
0
Divide
0
2.
0
1
3.
0
1
0
4 (default).
0
1
5.
1
0
6.
1
0
1
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1
0
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
0x1E1
4
Power down clock input section
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
3
Power down VCO clock interface
Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
2
Power down VCO and CLK
Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
0x1E1
1
Select VCO or CLK
Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
0
Bypass VCO divider
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Table 61. System
Reg.
Addr.
(Hex)
Bits
Name
Description
0x230
2
Power down SYNC
Powers down the SYNC function.
0: normal operation of the SYNC function (default).
1: powers down SYNC circuitry.
1
Power down distribution reference
Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
0
Soft SYNC
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
0: same as SYNC high (default).
1: same as SYNC low.
Table 62. Update All Registers
Reg.
Addr
(Hex)
Bits
Name
Description
0x232
0
Update all registers
This bit must be set to 1 to transfer the contents of the buffer registers into the active
registers. This bit is self-clearing; that is, it does not have to be set back to 0.
1 (self-clearing): updates all active registers to the contents of the buffer registers.
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