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| 型號： | AD9517-1ABCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 59/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.5GHZ VCO 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.65GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
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AD9517-1
Data Sheet
Rev. E | Page 62 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x017
[1:0]
Antibacklash
1
0
Antibacklash Pulse Width (ns)
pulse width
0
2.9 (default). This is the recommended setting; it does not normally need to be changed.
0
1
1.3. This setting may be necessary if the PFD frequency > 50 MHz.
1
0
6.0.
1
2.9.
0x018
[6:5]
Lock detect
counter
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
5
PFD Cycles to Determine Lock
0
5 (default).
0
1
16.
1
0
64.
1
255.
4
Digital lock detect
window
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
3
Disable digital
Digital lock detect operation.
lock detect
0: normal lock detect operation (default).
1: disables lock detect.
[2:1]
VCO cal divider
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
2
1
VCO Calibration Clock Divider
0
2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R.
0
1
4. This setting is fine for PFD frequencies < 25 MHz.
1
0
8. This setting is fine for PFD frequencies < 50 MHz.
1
16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time.
0
VCO cal now
Bit used to initiate the VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate
calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0b
(if not zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1b, followed by another
update bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the PLL losing lock.
The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration.
0x019
[7:6]
R, A, B counters
7
6
Action
SYNC pin reset
0
Does nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
Does nothing on SYNC.
[5:3]
R path delay
R path delay (default = 0x00) (see
[2:0]
N path delay
N path delay (default = 0x00) (see
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9517-1BCPZ | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:CLOCK GEN 12-OUTPUT VCO LFCSP-48 |
| AD9517-1BCPZ-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9517-1BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9517-2A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9517-2A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9517-2ABCPZ | 功能描述:IC CLOCK GEN 2.2GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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