參數(shù)資料
型號(hào)： AD9518-0ABCPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 63/64頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN 6CH 2.8GHZ 48LFCSP
標(biāo)準(zhǔn)包裝： 750
類(lèi)型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.95GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
AD9518-0
Data Sheet
Rev. C | Page 8 of 64
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ABSOLUTE TIME JITTER
Application example based on a typical
setup where the reference source is clean,
so a wider PLL loop bandwidth is used;
reference = 15.36 MHz; R = 1
VCO = 2.95 GHz; LVPECL = 491.52 MHz; PLL LBW = 75 kHz
148
fs rms
Integration BW = 200 kHz to 10 MHz
342
fs rms
Integration BW = 12 kHz to 20 MHz
VCO = 2.95 GHz; LVPECL = 122.88 MHz; PLL LBW = 75 kHz
212
fs rms
Integration BW = 200 kHz to 10 MHz
320
fs rms
Integration BW = 12 kHz to 20 MHz
VCO = 2.70 GHz; LVPECL = 122.88 MHz; PLL LBW = 187 kHz
184
fs rms
Integration BW = 200 kHz to 10 MHz
304
fs rms
Integration BW = 12 kHz to 20 MHz
VCO = 2.70 GHz; LVPECL = 61.44 MHz; PLL LBW = 187 kHz
221
fs rms
Integration BW = 200 kHz to 10 MHz
345
fs rms
Integration BW = 12 kHz to 20 MHz
VCO = 2.58 GHz; LVPECL = 61.44 MHz; PLL LBW = 75 kHz
210
fs rms
Integration BW = 200 kHz to 10 MHz
334
fs rms
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ABSOLUTE TIME JITTER
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 19.44 MHz; R = 1
VCO = 2.80 GHz; LVPECL = 155.52 MHz; PLL LBW = 12.8 kHz
513
fs rms
Integration BW = 12 kHz to 20 MHz
VCO = 2.95 GHz; LVPECL = 77.76 MHz; PLL LBW = 12.8 kHz
544
fs rms
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ABSOLUTE TIME JITTER
Application example based on a typical
setup using an external 245.76 MHz VCXO
(Toyocom TCO-2112); reference = 15.36 MHz;
R = 1
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
54
fs rms
Integration BW = 200 kHz to 5 MHz
77
fs rms
Integration BW = 200 kHz to 10 MHz
109
fs rms
Integration BW = 12 kHz to 20 MHz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
79
fs rms
Integration BW = 200 kHz to 5 MHz
114
fs rms
Integration BW = 200 kHz to 10 MHz
163
fs rms
Integration BW = 12 kHz to 20 MHz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
124
fs rms
Integration BW = 200 kHz to 5 MHz
176
fs rms
Integration BW = 200 kHz to 10 MHz
259
fs rms
Integration BW = 12 kHz to 20 MHz
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