參數(shù)資料
型號: AD9518-4ABCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 11/64頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 6CH 1.8GHZ 48LFCSP
標準包裝: 750
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.8GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
Data Sheet
AD9518-4
Rev. B | Page 19 of 64
–120
–160
–150
–140
–130
1k
100M
10M
1M
100k
10k
PH
A
S
E
N
O
ISE
(
d
B
c/
H
z)
FREQUENCY (Hz)
06
43
3-
2
08
Figure 23. Phase Noise (Absolute) Clock Generation; Internal VCO at
1.475 GHz; PFD = 15.36 MHz; LBW = 135 kHz; LVPECL Output = 122.88 MHz
–90
–100
–110
–120
–130
–140
–150
–160
1k
100M
10M
1M
100k
10k
PH
A
S
E
N
O
ISE
(
d
B
c/
H
z)
FREQUENCY (Hz)
06
43
3-
2
09
Figure 24. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 1.556 GHz;
PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
–120
–160
–150
–140
–130
1k
100M
10M
1M
100k
10k
PH
A
S
E
N
O
ISE
(
d
B
c/
H
z)
FREQUENCY (Hz)
06
43
3-
1
40
Figure 25. Phase Noise (Absolute); External VCXO (Toyocom TCO-2112) at
245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
1000
100
10
1
0.1
0.01
0.1
1
10
100
1000
IN
PU
T
J
IT
T
ER
A
M
PL
IT
U
D
E
(U
Ip
-p
)
JITTER FREQUENCY (kHz)
06433-
148
OC-48 OBJECTIVE MASK
AD9518
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
fOBJ
Figure 26. GR-253 Jitter Tolerance Plot
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