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| 型號(hào)： | AD9520-4/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9520-4 |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9520-4 |
| 主要屬性： | 1.4 ~ 1.8 GHz 輸出頻率 |
| 次要屬性： | 接受 CMOS、LVDS 或者最高 250 MHz 的 LVPECL 基準(zhǔn) |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁(yè)面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD9520-4BCPZ-REEL7-ND - IC CLOCK GEN 1.6GHZ VCO 64LFCSP AD9520-4BCPZ-ND - IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
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Data Sheet
AD9520-4
Rev. A | Page 19 of 80
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
15
I
3.3 V CMOS
CS
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up
resistor.
16
I
3.3 V CMOS
SCLK/SCL
Serial Control Port Clock Signal. This pin has an internal 30 kΩ pull-down resistor
in SPI mode, but is high impedance in IC mode.
17
I/O
3.3 V CMOS
SDIO/SDA
Serial Control Port Bidirectional Serial Data In/Out.
18
O
3.3 V CMOS
SDO
Serial Control Port Unidirectional Serial Data Out.
19, 59
I
GND
Ground Pins.
20
I
Three-level
logic
SP1
Select SPI or IC as the serial interface port and select the IC slave address in IC
mode. Three-level logic. This pin is internally biased for the open logic level.
21
I
Three-level
logic
SP0
Select SPI or IC as the serial interface port and select the IC slave address in IC
mode. Three-level logic. This pin is internally biased for the open logic level.
22
I
3.3 V CMOS
EEPROM
Setting this pin high selects the register values stored in the internal EEPROM to be
loaded at reset and/or power-up. Setting this pin low causes the AD9520 to load
the hard-coded default register values at power-up/reset (unless Register 0xB02[1]
is used. See the Soft Reset via the Serial Port section). This pin has an internal 30 kΩ
pull-down resistor. Note that, to guarantee proper loading of the EEPROM during
startup, a high-low-high pulse on the RESET pin should occur after the power supply
has stabilized.
23
I
3.3 V CMOS
RESET
Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
24
I
3.3 V CMOS
PD
Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.
25
O
LVPECL or
CMOS
OUT9 (OUT9A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
26
O
LVPECL or
CMOS
OUT9 (OUT9B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
27, 35,
46, 54
I
Power
VS_DRV
Output Driver Power Supply Pins. As a group, these pins can be set to either 2.5 V
or 3.3 V. All four pins must be set to the same voltage.
28
O
LVPECL or
CMOS
OUT10 (OUT10A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
29
O
LVPECL or
CMOS
OUT10 (OUT10B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
30
O
LVPECL or
CMOS
OUT11 (OUT11A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
31
O
LVPECL or
CMOS
OUT11 (OUT11B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
33
O
LVPECL or
CMOS
OUT6 (OUT6A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
34
O
LVPECL or
CMOS
OUT6 (OUT6B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
36
O
LVPECL or
CMOS
OUT7 (OUT7A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
37
O
LVPECL or
CMOS
OUT7 (OUT7B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
38
O
LVPECL or
CMOS
OUT8 (OUT8A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
39
O
LVPECL or
CMOS
OUT8 (OUT8B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
42
O
LVPECL or
CMOS
OUT5 (OUT5B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
43
O
LVPECL or
CMOS
OUT5 (OUT5A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
44
O
LVPECL or
CMOS
OUT4 (OUT4B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
45
O
LVPECL or
CMOS
OUT4 (OUT4A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
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| AD9520-5/PCBZ | 功能描述:BOARD EVAL FOR AD9520-5 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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