- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9674 > AD9573ARUZ (Analog Devices Inc)IC PCI CLCOK GEN 25MHZ 16TSSOP PDF資料下載
參數(shù)資料
| 型號： | AD9573ARUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI CLCOK GEN 25MHZ 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 系列： | PCI Express® (PCIe) |
| 類型： | 時鐘/頻率發(fā)生器，扇出緩沖器（分配） |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 輸入： | 晶體 |
| 輸出： | LVCMOS，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
AD9573
Rev. 0 | Page 10 of 12
evaluation board shows a good example (see the Ordering
Guide for information about the evaluation board).
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is the differential
output for the AD9573. LVDS uses a current mode output stage
with a factory programmed current level. The normal value
(default) for this current is 6.5 mA, which yields a 650 mV
output swing across a 100 Ω resistor.
The typical termination circuit for the LVDS outputs is shown
in Figure 11.
50
LVDS
100
0
75
00
-01
4
Figure 11. LVDS Output Termination
An alternative method of terminating the output to preserve output
swing but also minimize reflections is shown in Figure 12.
50
LVDS
200
0
75
00
-01
5
Figure 12. Alternative LVDS Output Termination
CMOS CLOCK DISTRIBUTION
The AD9573 provides a 33.33 MHz clock output, which is a
dedicated CMOS level. Whenever single-ended CMOS clocking
is used, some of the following general guidelines should be
followed.
Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
6 inches are recommended to preserve signal rise/fall times
and preserve signal integrity.
10
MICROSTRIP
GND
5pF
60.4
1.0 INCH
CMOS
0
75
00
-01
6
Figure 13. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS output of the AD9573 does not supply enough
current to provide a full voltage swing with a low impedance
resistive, far end termination, as shown in Figure 14. The far
end termination network should match the PCB trace
impedance and provide the desired switching point.
The reduced signal swing may still meet receiver input require-
ments in some applications. This can be useful when driving
long trace lengths on less critical nets.
VPULLUP = 3.3V
50
10
CMOS
3pF
100
0
75
00
-0
17
Figure 14. CMOS Output with Far-End Termination
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under
less than ideal operating conditions. In these application
circuits, the implementation and construction of the PCB is as
important as the circuit design. Proper RF techniques must be
used for device selection, placement, and routing, as well as for
power supply decoupling and grounding to ensure optimum
performance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS3452W24-22PW | CONN RCPT 4POS BOX MNT W/PINS |
| MS3452W24-22P | CONN RCPT 4POS BOX MNT W/PINS |
| MAX3873AETP+ | IC RECOV/RETIME 2.5GBPS 20TQFN |
| MS3452L24-22P | CONN RCPT 4POS BOX MNT W/PINS |
| MS3101E32-15P | CONN RCPT 8POS FREE HNG W/PINS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9573ARUZ-RL7 | 功能描述:IC PCI CLCOK GEN 25MHZ 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9573-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs |
| AD9574BCPZ | 功能描述:IC PLL CLOCK GEN 25MHZ 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 類型:* PLL:帶旁路 輸入:時鐘 輸出:CMOS，HCSL，HSTL，LVDS 電路數(shù):1 比率 - 輸入:輸出:2：7 差分 - 輸入:輸出:是/是 頻率 - 最大值:312.5MHz 分頻器/倍頻器:是/是 電壓 - 電源:2.97 V ~ 3.63 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:48-LFCSP-WQ（7x7） 標(biāo)準(zhǔn)包裝:1 |
| AD9574BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN 25MHZ 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:* PLL:帶旁路 輸入:時鐘 輸出:CMOS，HCSL，HSTL，LVDS 電路數(shù):1 比率 - 輸入:輸出:2：7 差分 - 輸入:輸出:是/是 頻率 - 最大值:312.5MHz 分頻器/倍頻器:是/是 電壓 - 電源:2.97 V ~ 3.63 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:48-LFCSP-WQ（7x7） 標(biāo)準(zhǔn)包裝:750 |
| AD9575 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Network Clock Generator, Two Outputs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。