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參數(shù)資料
| 型號(hào)： | AD9617JR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Low Distortion, Precision, Wide Bandwidth Op Amp |
| 中文描述： | OP-AMP, 2200 uV OFFSET-MAX, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大小： | 140K |
| 代理商： | AD9617JR |
AD9617
–8–
REV. B
AC GAIN CHARACTERISTICS
Closed-loop bandwidth at high frequencies is determined pri-
marily by the roll-off of T(s). But circuit layout is critical to
minimize external parasitics which can degrade performance by
causing premature peaking and/or reduced bandwidth.
The inverting and noninverting dynamic characteristics are similar.
When driving the noninverting input, the inverting input capaci-
tance (C
I
) will cause the noninverting closed-loop bandwidth to
be higher than the inverting bandwidth for gains less than two
(2). In the remaining cases, inverting and noninverting responses
are nearly identical.
For best overall dynamic performance, the value of the feedback
resistor (R
F
) should be 400 ohms. Although bandwidth reduces
as closed-loop gain increases, the change is relatively small due
to low equivalent series input impedance, Z
S
. (See typical
performance charts.) The simplified equations governing the
device’s dynamic performance are shown below.
Closed-Loop Gain vs. Frequency:
(noninverting operation)
V
O
V
I
≈
1
+
R
F
R
I
s
t
1
+
R
S
R
I
+
1
(6)
where:
t
=
R
F
×
C
C
= 0.9
ns
(
R
F
= 400
)
Slew Rate
≈
V
O
R
F
KC
C
×
e
τ
/
R
F
KC
C
(7)
where:
K
=
1
+
R
S
R
I
Increasing Bandwidth at Low Gains
By reducing R
F
, wider bandwidth and faster pulse response can
be attained beyond the specified values, although increased
overshoot, settling time and possible ac peaking may result. As a
rule of thumb, overshoot and bandwidth will increase by 1%
and 8%, respectively, for a 5% reduction in R
F
at gains of
±
10.
Lower gains will increase these sensitivities.
Equations 6 and 7 are simplified and do not accurately model
the second order (open loop) frequency response term which is
the primary contributor to overshoot, peaking and nonlinear
bandwidth expansion. (See Open Loop Bode Plots.) The user
should exercise caution when selecting R
F
values much lower
than 400
. Note that a feedback resistor must be used in all
situations, including those in which the amplifier is used in a
noninverting unity gain configuration.
Increasing Bandwidth at High Gains
Closed loop bandwidth can be extended at high closed loop gain
by reducing R
F.
Bandwidth reduction is a result of the feedback
current being split between R
S
and R
I
. As the gain increases (for
a given R
F
), more feedback current is shunted through R
I
, which
reduces closed loop bandwidth (see Equation 6). To maintain
specified BW, the following equations can be used to approxi-
mate R
F
and R
I
for any gain from
±
l to
±
15.
R
F
= 424
±
8
G
(+ for inverting and – for noninverting)
(8)
R
I
≈
424
8
G
G
1
(noninverting)
(9)
R
I
≈
424
+
8
G
G = Closed Loop Gain
.
G
1
(inverting)
(10)
Bandwidth Reduction
The closed loop bandwidth can be reduced by increasing R
F.
Equations 6 and 7 can be used to determine the closed loop
bandwidth for any value R
F
. Do not connect a feedback capaci-
tor across R
F
, as this will degrade dynamic performance and
possibly induce oscillation.
DC Precision and Noise
Output offset voltage results from both input bias currents and
input offset voltage. These input errors are multiplied by the
noise gain term (1 + R
F
/R
I
) and algebraically summed at the
output as shown below.
V
O
=
V
IO
×
1
+
R
F
R
I
±
IBn
×
R
N
×
1
+
R
F
R
I
±
IBi
×
R
F
(11)
Since the inputs are asymmetrical, IBi and IBn do not correlate.
Canceling their output effects by making R
N
= R
F
i
R
I
will not
reduce output offset errors, as it would for voltage feedback
amplifiers. Typically, IBn is 5
μ
A and V
IO
is +0.5 mV (I sigma =
0.3 mV), which means that the dc output error can be reduced
by making R
N
≈
100
. Note that the offset drift will not change
significantly because the IBn TC is relatively small. (See specifi-
cation table.)
IBi
IBn
R
I
R
N
R
F
V
OUT
Figure 15. Output Offset Voltage
10
–55
8
C
I
m
A
5
0
–5
–10
25
8
C
125
8
C
0
0.5
1.0
–0.5
–1.0
V
I
IBi
V
IO
IBn
Figure 16. DC Accuracy
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