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AD9630
–3–
REV. B
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltages (
±
V
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
7 V
Continuous Output Current
2
. . . . . . . . . . . . . . . . . . . . . 70 mA
Temperature Range over Which Specifications Apply
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . +300
°
C
Storage Temperature
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Junction Temperature
3
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
°
C
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Output is short-circuit protected to ground, but not to supplies. Prolonged short
circuit to ground may affect device reliability.
3
Typical thermal impedances (part soldered onto board): Plastic DIP (N):
θ
JA
=
110
°
C/W;
θ
JC
= 30
°
C/W; SOIC (R):
θ
JA
= 155
°
C/W;
θ
JC
= 40
°
C/W.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD9630AN
AD9630AR
AD9630AR-REEL –40
°
C to +85
°
C 13
"
Tape and Reel SO-8
–40
°
C to +85
°
C 8-Lead Plastic DIP N-8
–40
°
C to +85
°
C 8-Lead SOIC
SO-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9630 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
EXPLANATION OF TEST LEVELS
Test Level
I
100% Production tested.
II
100% Production tested at +25
°
C and sample tested at
specified temperatures. AC testing of AN and AR grades
done on sample basis only.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V
Typical value.
VI S Versions are 100% production tested at temperature
extremes. Other grades are sample tested at extremes.
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
NC = NO CONNECT
AD9630
NC
NC
NC
NC
100
(5%, 0.25W)
24
V
(5%, 0.25W)
+5V
–5.2V
0.1
m
F
0.1
m
F
AD9630 Burn-In Circuit
THEORY OF OPERATION
The AD9630 is a wide-bandwidth, closed-loop, unity-gain
buffer that makes use of a new voltage-feedback architecture.
This architecture brings together wide bandwidth and high slew
rate along with exceptional dc linearity. Most previous wide-
bandwidth buffers achieved their bandwidth by utilizing an
open-loop topology which sacrificed both dc linearity and fre-
quency distortion when driven into low load impedances. The
design’s high loop correction factor radically improves dc lin-
earity and distortion characteristics without diminishing
bandwidth. This, in combination with high slew rate, results in
exceptionally low distortion over a wide frequency range.
The AD9630 is an excellent choice to drive high speed and high
resolution analog-to-digital converters. Its output stage is de-
signed to drive high speed flash converters with minimal or no
series resistance. A current booster built into the output driver
helps to maintain low distortion.
Parasitic or load capacitance (>7 pF) connected directly to the
AD9630 output will result in frequency peaking. A small series
resistor (R
S
) connected between the buffer output and capaci-
tive load will negate this effect. Figure 1 shows the optimal value
of R
S
as a function of C
L
to obtain the flattest frequency re-
sponse. Figure 2 illustrates frequency response for various
capacitive loads utilizing the recommended R
S
.
C
L
– pF
50
40
00
100
20
R
S
V
40
60
80
30
20
10
7
R
S
C
L
200
V
"R"
NO
R
S
NEEDED
WHEN
C
L
<
7pF;
FOR
C
L
>
30pF,
"R"
CAN
BE
OMITTED
Figure 1. Recommended R
S
vs. C
L
WARNING!
ESD SENSITIVE DEVICE