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| 型號： | AD9633-125EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9633 |
| 標準包裝： | 1 |
| 系列： | * |
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AD9633
Data Sheet
Rev. 0 | Page 24 of 40
3.0
If the internal reference of the AD9633 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 59 shows
how the internal reference voltage is affected by loading.
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
0
2.5
2.0
1.5
1.0
0.5
V
RE
F
E
R
RO
R
(
%
)
LOAD CURRENT (mA)
INTERNAL VREF = 1V
10
07
3-
06
1
Figure 59. VREF Error vs. Load Current
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 60 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
10
07
3-
0
62
4
–8
–40
85
V
REF
E
R
RO
R
(
m
V
)
TEMPERATURE (°C)
–6
–4
–2
0
2
–15
10
35
60
Figure 60. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 53). The internal buffer generates the
positive and negative full-scale references for the ADC core. There-
fore, the external reference must be limited to a maximum of 1.0 V.
It is not recommended to leave the SENSE pin floating.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9633 sample clock inputs,
CLK+ and CLK, with a differential signal. The signal is typi-
cally ac-coupled into the CLK+ and CLK pins via a transformer
or capacitors. These pins are biased internally (see Figure 47)
and require no external bias.
Clock Input Options
The AD9633 has a flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is of
the most concern, as described in the Jitter Considerations
section.
ing the AD9633 (at clock rates up to 1 GHz prior to internal CLK
divider). A low jitter clock source is converted from a single-ended
signal to a differential signal using either an RF transformer or an
RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1 GHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the AD9633 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9633 while
preserving the fast rise and fall times of the signal that are criti-
cal to achieving low jitter performance. However, the diode
capacitance comes into play at frequencies above 500 MHz.
Care must be taken in choosing the appropriate signal limiting
diode.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
1
007
3-
06
4
Figure 61. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1F
CLOCK
INPUT
0.1F
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
1
007
3-
0
65
Figure 62. Balun-Coupled Differential Clock (Up to 1 GHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
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