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參數(shù)資料
| 型號： | AD9648-125EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/44頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD AD9648-125 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 2 Vpp |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9648 |
| 已供物品： | 板 |
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AD9648
Rev. 0 | Page 34 of 44
HARDWARE INTERFACE
The pins described in Table 15 comprise the physical interface
between the user programming device and the serial port of the
AD9648. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9648 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to DRVDD or ground
during device power-on, they are associated with a specific
function. Table 16 describes the strappable functions supported
on the AD9648.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, and the PDWN pin
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use the
pins as static control lines for the duty cycle stabilizer, output
data format, and power-down feature control. In this mode, the
CSB chip select bar should be connected to AVDD, which
disables the serial port interface.
When the device is in SPI mode, the PDWN and OEB Pins (if
enabled) remain active. For SPI control of output enable and
power-down, the OEB and PDWN pins should be set to their
default states.
Table 16. Mode Selection
Pin
External Voltage
Configuration
SDIO/DCS
DRVDD (default)
Duty cycle stabilizer enabled
AGND
Duty cycle stabilizer disabled
SCLK/DFS
DRVDD
Twos complement enabled
AGND (default)
Offset binary enabled
OEB
DRVDD
Outputs in high impedance
AGND (default)
Outputs enabled
PDWN
DRVDD
Chip in power-down or
standby
AGND (default)
Normal operation
SPI ACCESSIBLE FEATURES
Table 17 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9648 part-specific features are described in detail
following Table 18, the external memory map register table.
Table 17. Features Accessible Using the SPI
Feature Name
Description
Mode
Allows the user to set either power-down mode
or standby mode
Clock
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the sync
Offset
Allows the user to digitally adjust the
converter offset
Test I/O
Allows the user to set test modes to have
known data on output bits
Output Mode
Allows the user to set the output mode
including LVDS
Output Phase
Allows the user to set the output clock polarity
Output Delay
Allows the user to vary the DCO delay
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