參數(shù)資料
型號(hào): AD9648BCPZRL7-125
廠商: Analog Devices Inc
文件頁(yè)數(shù): 44/44頁(yè)
文件大小: 0K
描述: IC ADC 14BIT 125MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: LVDS,并聯(lián),串行,SPI
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,2 個(gè)差分
AD9648
Rev. 0 | Page 9 of 44
TIMING SPECIFICATIONS
Table 5.
Parameter
Description
Limit
Unit
SYNC TIMING
REQUIREMENTS
t
SSYNC
SYNC to rising edge of CLK+ setup time
0.24
ns typ
t
HSYNC
SYNC to rising edge of CLK+ hold time
0.40
ns typ
SPI TIMING
REQUIREMENTS
t
DS
Setup time between the data and the rising edge of SCLK
2
ns min
t
DH
Hold time between the data and the rising edge of SCLK
2
ns min
t
CLK
Period of the SCLK
40
ns min
t
S
Setup time between CSB and SCLK
2
ns min
t
H
Hold time between CSB and SCLK
2
ns min
t
HIGH
SCLK pulse width high
10
ns min
t
LOW
SCLK pulse width low
10
ns min
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an output relative
to the SCLK falling edge
10
ns min
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative
to the SCLK rising edge
10
ns min
Timing Diagrams
tPD
tSKEW
tCH
tDCO
tCLK
N – 16
N – 17
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
N – 15
N – 14
N – 13
N – 12
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
tA
09975-
002
Figure 2. CMOS Default Output Mode Data Output Timing
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