參數(shù)資料
型號(hào)： AD9649BCPZRL7-65
廠商： Analog Devices Inc
文件頁數(shù)： 2/32頁
文件大小： 0K
描述： IC ADC 14BIT 65MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 87.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
AD9649
Rev. 0 | Page 10 of
32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
CLK+
2
CLK–
3
AVDD
4
CSB
5
SCLK/DFS
6
SDIO/PDWN
7
D0 (LSB)
8
D1
24 AVDD
23 MODE/OR
22 DCO
21 D13 (MSB)
20 D12
19 D11
18 D10
17 D9
9
D
2
1
0
D
3
1
D
4
1
2
D
5
1
3
D
R
V
D
1
4
D
6
1
5
D
7
1
6
D
8
3
2
A
V
D
3
1
V
IN
+
3
0
V
IN
–
2
9
A
V
D
2
8
R
B
IA
S
2
7
V
C
M
2
6
S
E
N
S
E
2
5
V
R
E
F
TOP VIEW
(Not to Scale)
AD9649
08
53
9-
00
3
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE ANALOG GROUND
PLANE OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND MAXIMIZE
THE HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
0 (EP)
GND
Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog
ground of the customer’s PCB to ensure proper functionality and maximize the heat dissipation, noise,
and mechanical strength benefits.
1, 2
CLK+, CLK
Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
3, 24, 29, 32
AVDD
1.8 V Supply Pin for the ADC CORE Domain.
4
CSB
SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
5
SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6
SDIO/PDWN
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down.
See Table 14 for details.
7 to 12, 14 to 21
D0 (LSB) to
D13 (MSB)
ADC Digital Outputs.
13
DRVDD
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
22
DCO
Data Clock Digital Output.
23
MODE/OR
Chip Mode Select Input in SPI Mode (MODE).
Out-of-Range Digital Output in SPI Mode or in Non-SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100).
Chip stand-by (SPI Register 0x08, Bits[7:5] = 101).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111).
In non-SPI mode, the pin operates only as an out-of-range (OR) digital output.
25
VREF
1.0 V Voltage Reference Input/Output. See Table 10.
26
SENSE
Reference Mode Selection. See Table 10.
27
VCM
Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
28
RBIAS
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
30, 31
VIN, VIN+
ADC Analog Inputs.
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