參數(shù)資料
型號(hào): AD9660KR
廠商: ANALOG DEVICES INC
元件分類: 其它接口
英文描述: 200 MHz Laser Diode Driver with Light Power Control
中文描述: SPECIALTY INTERFACE CIRCUIT, PDSO28
封裝: PLASTIC, SOIC-28
文件頁(yè)數(shù): 10/12頁(yè)
文件大小: 256K
代理商: AD9660KR
REV. 0
–10–
AD9660
Offset Current Generator
The offset current source allows the user to inject a fixed,
uncalibrated current into the laser diode. The offset current
source is set by an external resistor connected between OFF-
SET CURRENT SET and +V
S
, and is controlled by OFFSET
PULSE. See Figure 2 for a transfer function of the offset cur-
rent source.
The offset current may be used to increase the output current
provided by the bias and/or write loops after calibration. Alter-
natively, the offset current may be added during the calibration
of the bias loop and switched off after calibration to drop the
bias current below the knee of the laser diode power curve.
This is illustrated in Figure 10.
4
3
0
0
120
20
O
40
100
2
1
CONSTANT WRITE POWER
BIAS CALIBRATION POWER
0
°
C CASE
25
C
CASE
50
°
C CASE
BIAS
OFFSET
2
60
80
1
WITH OFFSET CURRENT TURNED OFF,
BIAS CURRENT IS BELOW THE KNEE OF THE LASER DIODE
2
OFFSET CURRENT TURNED ON DURING BIAS-CAL
MOD
BIAS
1
FORWARD CURRENT – mA
OPERATING
BIAS LEVEL
Figure 10. Laser Diode Current-to-Optical Power Curve
Illustrating Bias Below Diode Knee
AD9660 Layout Considerations
As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as pos-
sible, and isolated from digital signals to avoid coupling in noise.
In particular, digital lines should be isolated from OUTPUT,
PIN SENSE, WRITE LEVEL, and BIAS LEVEL traces. Digi-
tal signal paths should also be kept short, and run lengths
matched to avoid propagation delay mismatch.
Layout of the ground and power supply circuits is also critical.
A single, low impedance ground plane will reduce noise on the
circuit ground. Power supplies should be capacitively coupled
to the ground plane to reduce noise in the circuit. 0.1
μ
F sur-
face mount capacitors, placed as close as possible to the
AD9660 +V
S
connections meet this requirement. Multilayer
circuit boards allow designers to lay out signal traces without
interrupting the ground plane, and provide low impedance
power planes to further reduce noise.
Minimizing the Impedance of the Output Current Path
Because of the very high current slew that the AD9660 is
capable of producing (70+ mA in 1.5 ns), the inductance of the
output current path to and from the laser diode is critical. A
good layout of the output current path will yield high quality
light pulses with rise times of about 1.5 ns and less than 5%
overshoot. A poor layout can result in significant overshoot and
ringing. The most important guideline for the layout is to mini-
mize the impedance (mostly inductance) of the output current
path to the laser. It is important to recognize that the laser cur-
rent path is a closed loop. The figure illustrates the path that
current travels: (1) from the output pins of the AD9660 to the
anode of the laser, (2) through the laser to the cathode
(ground), (3) through the return path, (4) through the 0.1
μ
F
bypass capacitors back to the +V
S
pins of the AD9660 where (5)
the current travels through the output driver circuitry of the
AD9660, and back to the output pins. The inductance of this
loop can be minimized by placing the laser as close to the
AD9660 as possible to keep the loop short, and by placing the
send and return paths on adjacent layers of the PC board to take
advantage of mutual coupling of the path inductances. This
mutual coupling effect is the most important factor in reducing
inductance in the current path.
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