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AD9661A
REV. 0
–4–
PIN DE SCRIPT IONS
Pin
Function
OUT PUT
Analog laser diode current output. Connect to cathode of laser diode, anode connected to +V
S
externally.
POWER LEVEL
Analog voltage input, V
REF
to V
REF
+ 1.6 V. Output current is set proportional to the POWER LEVEL
I
MONITOR
=
V
POWER LEVEL
R
GAIN
+
50
during calibration as follows:
±
V
REF
CAL
T T L/CMOS compatible, feedback loop T /H control signal. Logic LOW enables calibration mode, and
the feedback loop T /H goes into track mode 13 ns after (the aperture delay) PULSE goes logic HIGH
(there is no aperture delay if PULSE goes high before CAL transitions to a LOW level). Logic HIGH dis-
ables the T /H and immediately places it in hold mode. PULSE should be held HIGH while calibrating.
Floats logic HIGH.
HOLD
External hold capacitor for the bias loop T /H. Approximate droop in the output current while CAL is
±
I
OUT
=
18
×
10
t
HOLD
C
HOLD
1
2
π
(550
)
C
HOLD
logic HIGH is:
Bandwidth of the loop is:
BW
≈
PULSE
T T L /CMOS compatible, current control signal. Logic HIGH supplies I
OUT
to the laser diode. Logic
LOW turns I
OUT
off. Floats logic HIGH.
T T L /CMOS compatible, current control signal. Logic LOW supplies I
OUT
to the laser diode. Logic
HIGH turns I
OUT
off. Floats logic HIGH.
Analog current input, I
MONIT OR
, from PIN photo detector diode. SENSE IN should be connected to the
anode of the PIN diode, with the PIN cathode connected to +V
S
or another positive voltage. Voltage at
SENSE IN varies slightly with temperature and current, but is typically 1.0 V.
External connection for the feedback network of the transimpedance amplifier. External feedback network,
R
GAIN
and C
GAIN
, should be connected between GAIN and POWER MONIT OR. See text for choosing
values.
Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from
photo diode, I
MONIT OR
.
T T L/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH
disables the current outputs to the laser diode, and drives the voltage on the hold capacitors close to V
REF
(minimizes the output current when the device is re-enabled). DISABLE floats logic HIGH.
Analog Voltage output, internal bandgap voltage reference, ~1.8 V, provided to user for power level offset.
Power Supply, nominally +5 V. All +V
S
connections should be tied together externally.
Ground reference. All GROUND connections should be tied together externally.
Analog input to the on board level shift circuit. Input Range 0.1 V – 1.6 V.
Voltage output from on board level shift circuit. Connect to POWER LEVEL externally to use the on
board level shift circuit. Output voltage is V
LEVEL SHIFT OUT
= V
LEVEL SHIFT IN
+V
REF
.
PULSE 2
SENSE IN
GAIN
POWER MONIT OR
DISABLE
V
REF
+V
S
GROUND
LEVEL SHIFT IN
LEVEL SHIFT OUT
PIN ASSIGNME NT S
AD9661AKR
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PULSE2
DNC
V
REF
LEVEL SHIFT IN
GAIN
SENSE INPUT
GROUND
+V
S
GROUND
HOLD
POWER LEVEL
DISABLE
+V
S
GROUND
OUTPUT
GROUND
OUTPUT
GROUND
OUTPUT
GROUND
OUTPUT
GROUND
+V
S
GROUND
CAL
PULSE1
POWER MONITOR
LEVEL SHIFT OUT