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參數(shù)資料
| 型號(hào)： | AD96685BP-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Ultrafast Comparators |
| 中文描述： | COMPARATOR, 3000 uV OFFSET-MAX, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | AD96685BP-REEL |
AD96685/AD96687
–5–
REV. C
APPLICAT IONS INFORMAT ION
T he AD96685/87 comparators are very high speed devices.
Consequently, high speed design techniques must be employed
to achieve the best performance. T he most critical aspect of any
AD96685/87 design is the use of a low impedance ground
plane.
Another area of particular importance is power supply
decoupling. Normally, both power supply connections should
be separately decoupled to ground through 0.1
μ
F ceramic and
0.001
μ
F mica capacitors. T he basic design of comparator cir-
cuits makes the negative supply somewhat more sensitive to
variations. As a result more attention should be placed on insur-
ing a “clean” negative supply.
T he LAT CH ENABLE input is active LOW (latched). If the
latching function is not used, the LAT CH ENABLE input
should be grounded (ground is an ECL logic HIGH). T he
LATCH ENABLE
input of the AD96687 should be tied to
–2.0 V or left “floating,” to disable the latching function. An
alternate use of the LAT CH ENABLE input is as a hysteresis
control input. By varying the voltage at the LAT CH ENABLE
input for the AD96685 and the differential voltage between both
latch inputs for the AD96687, small variations in the hysteresis
can be achieved.
Occasionally, one of the two comparator stages within the
AD96687 will not be used. T he inputs of the unused compara-
tor should not be allowed to “float.” T he high internal gain may
cause the output to oscillate (possibly affecting the other com-
parator which is being used) unless the output is forced into a
fixed state. T his is easily accomplished by insuring that the two
inputs are at least one diode drop apart, while also grounding
the LAT CH ENABLE input.
T he best performance will be achieved with the use of proper
ECL terminations. T he open-emitter outputs of the
AD96685/87 are designed to be terminated through 50
resis-
tors to –2.0 V, or any other equivalent ECL termination. If high
speed ECL signals must be routed more than a few centimeters,
MicroStrip or StripLine techniques may be required to insure
proper transition times and prevent output ringing.
T he AD96685/87 have been specifically designed to reduce
propagation delay dispersion over an input overdrive range of
100 mV to 1 V. Propagation delay dispersion is the change in
propagation delay which results from a change in the degree of
overdrive (how far the switching point is exceeded by the input).
T he overall result is a higher degree of timing accuracy since the
AD96685/87 is far less sensitive to input variations than most
comparator designs.
Typical Applications
HIGH SPE E D SAMPLING CIRCUIT
HIGH SPE E D WINDOW COMPARAT OR
ORDE RING GUIDE
T emperature
Range
Package
Options
Model
T ype
Description
AD96685BH
AD96685BP
AD96685BQ
AD96685BR
AD96685BP-REEL
AD96685T Q
AD96687BP
AD96687BQ
AD96687BR
AD96687BR-REEL
AD96687T Q
Single
Single
Single
Single
Single
Single
Dual
Dual
Dual
Dual
Dual
–25
°
C to +85
°
C
–25
°
C to +85
°
C
–25
°
C to +85
°
C
–25
°
C to +85
°
C
–25
°
C to +85
°
C
–55
°
C to +125
°
C
–25
°
C to +85
°
C
–25
°
C to +85
°
C
–25
°
C to +85
°
C
–25
°
C to +85
°
C
–55
°
C to +125
°
C
10-Pin Can, Industrial
20-Pin PLCC, Industrial
16-Pin DIP, Industrial
16-Pin SOIC, Industrial
20-Pin PLCC, Industrial
16-Pin DIP, Extended T emperature
20-Pin PLCC, Industrial
16-Pin DIP, Industrial
16-Pin SOIC, Industrial
16-Pin SOIC, Industrial
16-Pin DIP, Extended T emperature
H-10A
P-20A
Q-16
R-16A
P-20A
Q-16
P-20A
Q-16
R-16A
R-16A
Q-16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD96685BQ | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Ultrafast Comparators |
| AD96685BR | 功能描述:IC COMP SNGL ULTRA-FAST 16-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:通用 元件數(shù):1 輸出類(lèi)型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類(lèi)型:表面貼裝 包裝:管件 其它名稱(chēng):Q3554586 |
| AD96685BR-REEL | 功能描述:IC COMP SNGL ULTRA-FAST 16-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:通用 元件數(shù):1 輸出類(lèi)型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類(lèi)型:表面貼裝 包裝:管件 其它名稱(chēng):Q3554586 |
| AD96685BRZ | 功能描述:IC COMP SNGL ULTRA-FAST 16-SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:通用 元件數(shù):1 輸出類(lèi)型:CMOS，開(kāi)路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標(biāo)準(zhǔn)）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標(biāo)準(zhǔn)）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類(lèi)型:表面貼裝 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:1268 (CN2011-ZH PDF) 其它名稱(chēng):*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| AD96685BRZ-REEL | 功能描述:IC COMP SNGL ULTRA-FAST 16-SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:通用 元件數(shù):1 輸出類(lèi)型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類(lèi)型:表面貼裝 包裝:管件 其它名稱(chēng):Q3554586 |
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