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參數(shù)資料
型號(hào)： AD9705-DPG2-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/44頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9705
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9704/AD9705/AD9706/AD9707
Data Sheet
Rev. B | Page 36 of 44
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.0 V for an IOUTFS = 2 mA to 0.8 V for an IOUTFS = 1 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
ADJUSTABLE OUTPUT COMMON MODE
The AD9704/AD9705/AD9706/AD9707 provide the ability to set
the output common mode to a value other than ACOM via Pin 19
(OTCM). This extends the compliance range of the outputs and
facilitates interfacing the output of the AD9704/AD9705/AD9706/
AD9707 to components that require common-mode levels other
than 0 V. The OTCM pin demands dynamically changing current
and should be driven by a low source impedance to prevent a
common-mode signal from appearing on the DAC outputs. The
OTCM pin also serves to change the DAC bias voltages in the
parts, allowing them to run at higher dc output bias voltages.
When running the bias voltage below 0.9 V and an AVDD of
3.3 V, the parts perform optimally when the OTCM pin is tied
to ground. When the dc bias increases above 0.9 V, set the OTCM
pin at 0.5 V for optimal performance. Keep the maximum dc
bias on the DAC output at or below 1.2 V when the supply is
3.3 V. When the supply is 1.8 V, keep the dc bias close to 0 V
and connect the OTCM pin directly to ground. Note that setting
OTCM to a voltage greater than ACOM allows the peak of the
output signal to be closer to the positive supply rail. To prevent
distortion in the output signal due to limited available headroom,
the common-mode level must be chosen such that the following
expression is satisfied:
AVDD VOTCM > 1.8 V
(9)
DIGITAL INPUTS
The AD9707, AD9706, AD9705, and AD9704 have data inputs of
14, 12, 10, and 8 bits, respectively, and each has a clock input.
The parallel data inputs can follow standard positive binary or
twos complement coding. IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a
complementary output with the full-scale current split between
the two outputs as a function of the input code.
DIGITAL
INPUT
DVDD
05
92
6-
0
78
Figure 79. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
175 MSPS. The clock can be operated at any duty cycle that meets
the specified latch pulse width. The setup and hold times can
also be varied within the clock cycle, as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
Deskew Mode
The AD9704/AD9705/AD9706/AD9707 provides an optional
deskew mode. Turning on the deskew mode can improve the skew
glitch behavior of the DAC. With the deskew mode enabled, a one
CLK+/CLK clock cycle register delay is added to the digital input
path. By default, the DESKEW bit in the data register (0x02) is
set to 0, disabling the dskew mode.
CLOCK INPUT
A configurable clock input allows the device to be operated in a
single-ended or a differential clock mode. The mode selection
can be controlled either by the CMODE pin, if the device is in
pin mode; or through Register 0x02, Bit 2 (CLKDIFF) of the SPI
registers, if the SPI is enabled. Connecting CMODE to CLKCOM
selects the single-ended clock input. In this mode, the CLK+
input is driven with rail-to-rail swings, and the CLK input is
left floating. If CMODE is connected to CLKVDD, the differential
receiver mode is selected. In this mode, both inputs are high
impedance. Table 24 gives a summary of clock mode control.
There is no significant performance difference between the
clock input modes.
Table 24. Clock Mode Selection
SPI Disabled,
CMODE Pin
SPI Enabled,
Register 0x02, Bit 2
Clock Input Mode
CLKCOM
0
Single ended
CLKVDD
1
Differential
In differential input mode, the clock input functions as a high
impedance differential pair. The common-mode level of the
CLK+ and CLK inputs can vary from 0.75 V to 2.25 V, and the
differential voltage can be as low as 0.5 V p-p. This mode can be
used to drive the clock with a differential sine wave because the
high gain bandwidth of the differential inputs converts the sine
wave into a single-ended square wave internally.
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship
between the position of the clock edges and the time at which
the input data changes. To achieve the DAC performance specified
in this data sheet, data input (DB) and clock (CLK+/CLK) must
meet the setup and hold time requirements specified in the relevant
digital specifications.
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