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參數(shù)資料
| 型號： | AD9708-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9708 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時(shí)間： | 35ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9708 |
| 相關(guān)產(chǎn)品： | AD9708ARZRL-ND - IC DAC 8BIT 100MSPS 28-SOIC AD9708ARZ-ND - IC DAC 8BIT 100MSPS 28-SOIC AD9708ARUZRL7-ND - IC DAC 8BIT 100MSPS 28-TSSOP TR AD9708ARUZ-ND - IC DAC 8BIT 100MSPS 28-TSSOP AD9708ARURL7-ND - IC DAC 8BIT 100MSPS 28-TSSOP AD9708ARU-ND - IC DAC 8BIT 100MSPS 28-TSSOP AD9708AR-ND - IC DAC 8BIT 100MSPS 28-SOIC |
AD9708
–8–
REV. B
50pF
COMP1
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
0.1 F
+5V
REFIO
FS ADJ
2k
0.1 F
AD9708
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
Figure 13. Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 14. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1
F compensation capacitor is not required
since the internal reference is disabled, and the high input
impedance (i.e., 1 M
) of REFIO minimizes any loading of the
external reference.
50pF
COMP1
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
0.1 F
AVDD
REFIO
FS ADJ
RSET
AD9708
EXTERNAL
REF
IREF =
VREFIO/RSET
AVDD
REFERENCE
CONTROL
AMPLIFIER
VREFIO
Figure 14. External Reference Configuration
The AD9708 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a V-I converter, as shown
in Figure 14, such that its current output, IREF, is determined by
the ratio of the VREFIO and an external resistor, RSET, as stated
in Equation 4. The control amplifier allows a wide (10:1)
adjustment span of IOUTFS over a 2 mA to 20 mA range by setting
IREF between 62.5
A and 625 A. The wide adjustment span of
IOUTFS provides several application benefits. The first benefit
relates directly to the power dissipation of the AD9708, which is
proportional to IOUTFS (refer to the POWER DISSIPATION
section). The second benefit relates to the 20 dB adjustment,
which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 1.8 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as
a filter to reduce the noise contribution from the reference
amplifier. If IREF is fixed for an application, a 0.1
F ceramic chip
capacitor is recommended.
IREF can be varied for a fixed RSET by disabling the internal
reference and varying the common-mode voltage over its
compliance range of 1.25 V to 0.10 V. REFIO can be driven by
a single-supply amplifier or DAC, thus allowing IREF to be var-
ied for a fixed RSET. Since the input impedance of REFIO is
approximately 1 M
, a simple R-2R ladder DAC configured in
the voltage mode topology may be used to control the gain. This
circuit is shown in Figure 15 using the AD7524 and an external
1.2 V reference, the AD1580. Note another AD9708 could also
be used as the gain control DAC since it can also provide a
programmable unipolar output up to 1.2 V.
ANALOG OUTPUTS AND OUTPUT CONFIGURATIONS
The AD9708 produces two complementary current outputs,
IOUTA and IOUTB, which may be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load resistor,
RLOAD, as described in the DAC TRANSFER FUNCTION
section. Figure 16 shows the AD9708 configured to provide a
positive unipolar output range of approximately 0 V to +0.5 V
for a double terminated 50
cable for a nominal full-scale
current, IOUTFS, of 20 mA. In this case, RLOAD represents the
equivalent load resistance seen by IOUTA or IOUTB and is
equal to 25
. The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching RLOAD. Different
values of IOUTFS and RLOAD can be selected as long as the posi-
tive compliance range is adhered to.
AD9708
IOUTA
IOUTB 21
50
25
50
VOUTA = 0 TO +0.5V
IOUTFS = 20mA
22
Figure 16. 0 V to +0.5 V Unbuffered Voltage Output
Alternatively, an amplifier could be configured as an I-V converter
thus converting IOUTA or IOUTB into a negative unipolar
1.2V
50pF
COMP1
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
AVDD
REFIO
FS ADJ
RSET
AD9708
IREF =
VREF/RSET
AVDD
OPTIONAL
BANDLIMITING
CAPACITOR
VREF
VDD
RFB
OUT1
OUT2
AGND
DB7–DB0
AD7524
AD1580
0.1V TO 1.2V
Figure 15. Single-Supply Gain Control Circuit
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