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    參數(shù)資料
    型號(hào): AD9715BCPZRL7
    廠商: Analog Devices Inc
    文件頁數(shù): 7/80頁
    文件大小: 0K
    描述: IC DAC DUAL 10BIT LO PWR 40LFCSP
    產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
    DAC Architectures
    標(biāo)準(zhǔn)包裝: 750
    系列: TxDAC®
    位數(shù): 10
    數(shù)據(jù)接口: 串行
    轉(zhuǎn)換器數(shù)目: 2
    電壓電源: 模擬和數(shù)字
    功率耗散(最大): 86mW
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 40-VFQFN 裸露焊盤,CSP
    供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
    包裝: 帶卷 (TR)
    輸出數(shù)目和類型: 4 電流,單極
    采樣率(每秒): 125M
    AD9714/AD9715/AD9716/AD9717
    Rev. A | Page 15 of 80
    Pin No.
    Mnemonic
    Description
    31
    CMLI
    I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the
    on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is
    disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor
    (see the Using the Internal Termination Resistors section). The recommended value for this external resistor
    is 0 Ω.
    32
    FSADJQ/AUXQ
    Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-
    scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of
    Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
    Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC
    output.
    33
    FSADJI/AUXI
    Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is the full-
    scale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of
    Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
    Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC
    output.
    34
    REFIO
    Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
    reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
    35
    RESET/PINMD
    This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
    Pulse RESET high to reset the SPI registers to their default values.
    A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
    36
    SCLK/CLKMD
    Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
    Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
    DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the
    37
    SDIO/FORMAT
    Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
    Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
    (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
    twos complement input data format.
    38
    CS/PWRDN
    Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
    Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
    the SPI port.
    39
    DB11 (MSB)
    Digital Input (MSB).
    40
    DB10
    Digital Input.
    41 (EPAD)
    Exposed Pad
    (EPAD)
    The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the
    package corners is connected to this pad.
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