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| 型號(hào)： | AD9740ARUZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/32頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT 210MSPS 28-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | TxDAC® |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 145mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 210M |
| 配用： | AD9740ACP-PCBZ-ND - BOARD EVAL FOR AD9740ACP |
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AD9740
Rev. B | Page 19 of 32
AD9740
IOUTA
IOUTB
COPT
200
Ω
U1
VOUT = IOUTFS × RFB
IOUTFS = 10mA
RFB
200
Ω
22
21
02911-
034
Figure 36. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS,
POWER SUPPLY REJECTION
Many applications seek high speed and high performance
under less than ideal operating conditions. In these application
circuits, the implementation and construction of the printed
circuit board is as important as the circuit design. Proper RF
techniques must be used for device selection, placement, and
routing as well as power supply bypassing and grounding to
the recommended printed circuit board ground, power, and
signal plane layouts implemented on the AD9740 evaluation
board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9740 AVDD supply over this frequency range is shown in
FREQUENCY (MHz)
85
40
12
68
10
0
PSRR
(
d
B)
80
75
70
65
60
55
50
24
45
02911-035
Figure 37. Power Supply Rejection Ratio (PSRR)
Note that the ratio in Figure 37 is calculated as amps out/volts
in. Noise on the analog power supply has the effect of modulating
the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, is added in a nonlinear
manner to the desired IOUT. Due to the relative different size of
these switches, the PSRR is very code dependent. This can produce
a mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs occur when the full-scale current
is directed toward that output.
As a result, the PSRR measurement in Figure 37 represents a
worst-case condition in which the digital inputs remain static
and the full-scale output current of 20 mA is directed to the
DAC output being measured.
The following illustrates the effect of supply noise on the analog
supply. Suppose a switching regulator with a switching frequency
of 250 kHz produces 10 mV of noise and, for simplicity’s sake
(ignoring harmonics), all of this noise is concentrated at 250 kHz.
To calculate how much of this undesired noise appears as current
noise superimposed on the DAC’s full-scale current, IOUTFS, users
must determine the PSRR in dB using Figure 37 at 250 kHz. To
calculate the PSRR for a given RLOAD, such that the units of PSRR
are converted from A/V to V/V, adjust the curve in Figure 37 by
the scaling factor 20 Ω log (RLOAD). For instance, if RLOAD is 50 Ω,
then the PSRR is reduced by 34 dB (that is, PSRR of the DAC at
Proper grounding and decoupling should be a primary
objective in any high speed, high resolution system. The
AD9740 features separate analog and digital supplies and
ground pins to optimize the management of analog and digital
ground currents in a system. In general, AVDD, the analog
supply, should be decoupled to ACOM, the analog common, as
close to the chip as physically possible. Similarly, DVDD, the
digital supply, should be decoupled to DCOM as close to the
chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply can be
generated using the circuit shown in Figure 38. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
100
μF
ELECT.
0.1
μF
CER.
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
FERRITE
BEADS
AVDD
ACOM
10
μF–22μF
TANT.
02911-036
Figure 38. Differential LC Filter for Single 3.3 V Applications
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