I DV DD1 8 ( mA) 0" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AD9745-DPG2-EBZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 19/28闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC DAC DUAL 12BIT 72LFCSP
瑷�(sh猫)瑷�(j矛)璩囨簮锛� AD9747/6/5/3/1 DPG2 Eval Brd Schematic
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
DAC 鐨勬暩(sh霉)閲忥細 2
浣嶆暩(sh霉)锛� 12
閲囨ǎ鐜囷紙姣忕锛夛細 250M
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 骞惰伅(li谩n)
DAC 鍨嬶細 闆绘祦
宸ヤ綔婧害锛� -40°C ~ 85°C
宸蹭緵鐗╁搧锛� 鏉�
宸茬敤 IC / 闆朵欢锛� AD9745
AD9741/AD9743/AD9745/AD9746/AD9747
Data Sheet
Rev. A | Page 26 of 28
30
24
18
12
6
0
I DV
DD1
8
(
mA)
0
50
100
150
200
250
fDAC (MHz)
06569-
032
25
75
125
175
225
AD9747
AD9741
Figure 41. DVDD18 Current vs. fDAC
15
13
11
9
7
5
I CV
DD1
8
(
mA)
0
50
100
150
200
250
fDAC (MHz)
06569-
033
25
75
125
175
225
Figure 42. CVDD18 Current vs. fDAC
Figure 43 shows the power consumption for each power supply
domain as well as the total power consumption. Individual bars
within each group display the power in full active mode (blue)
vs. power for five increasing levels of power-down.
06569-
045
P
DI
S
(
mW
)
0
50
100
150
200
250
300
350
AVDD33
DVDD18
CVDD18
DVDD33
TOT PWR
FULL ACTIVE
DCO OFF
AUX OFF
DAC OFF
CLK OFF
BIAS OFF
Figure 43. Power Dissipation vs. Power-Down Mode
The overall power consumption is dominated by AVDD33 and
significant power savings can be achieved simply by disabling
the DAC outputs. Also, disabling the DAC outputs is a signifi-
cant way to conserve power and still maintain a fast wake-up
time. Full power-down disables all circuitry for minimum
power consumption. Note, however, that even in full power-
down, there is a small power draw (25 mW) due to incoming
data activity. To lower power consumption to near zero, all
incoming data activity must be halted.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
RBM25DRXN CONN EDGECARD 50POS DIP .156 SLD
STD24W-Q WIRE & CABLE MARKERS
RBM25DRXH CONN EDGECARD 50POS DIP .156 SLD
0210490211 CABLE JUMPER 1.25MM .030M 16POS
HL02220GTTR INDUCTOR 22NH 180MA 0402
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AD9745-EBZ 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters
AD9746 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters
AD9746BCPZ 鍔熻兘鎻忚堪:IC DAC DUAL 14B 250MSPS 72LFCSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k
AD9746BCPZRL 鍔熻兘鎻忚堪:IC DAC DUAL 14B 250MSPS 72-LFCSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k
AD9746-DPG2-EBZ 鍔熻兘鎻忚堪:IC DAC DUAL 14BIT 72LFCSP RoHS:鏄� 椤炲垾:绶ㄧ▼鍣�锛岄枊(k膩i)鐧�(f膩)绯荤当(t菕ng) >> 瑭�(p铆ng)浼版澘 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 (DAC) 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- DAC 鐨勬暩(sh霉)閲�:4 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:- 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛孲PI? 瑷�(sh猫)缃檪(sh铆)闁�:3µs DAC 鍨�:闆绘祦/闆诲 宸ヤ綔婧害:-40°C ~ 85°C 宸蹭緵鐗╁搧:鏉� 宸茬敤 IC / 闆朵欢:MAX5581