參數(shù)資料
型號(hào): AD974BNZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 3/20頁(yè)
文件大?。?/td> 0K
描述: IC DAS 16BIT 4CH 200KSPS 28DIP
標(biāo)準(zhǔn)包裝: 13
類(lèi)型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 16 b
采樣率(每秒): 200k
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 通孔
封裝/外殼: 28-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 28-PDIP
包裝: 管件
配用: EVAL-AD974CB-ND - BOARD EVAL FOR AD974
REV. A
AD974
–11–
EXTERNAL CONTINUOUS CLOCK DATA READ AFTER
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 8 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a con-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK either while
CS is high or while both CS and R/C are
low.
With a continuous clock the
CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock,
while a conversion is occurring, can increase the DNL and
Transition Noise of the AD974.
After a conversion is complete, indicated by
BUSY returning
high, the result of that conversion can be read while
CS is low
and R/
C is high. In Figure 8 clock pulse #0 is used to enable the
generation of a SYNC pulse. The SYNC pulse is actually clocked
out approximately 40 ns after the rising edge of clock pulse #1.
The SYNC pulse will be valid on the falling edge of clock pulse
#1 and the rising edge of clock pulse #2. The MSB will be valid
on the falling edge of clock pulse #2 and the rising edge of clock
pulse #3. The LSB will be valid on the falling edge of clock
pulse #17 and the rising edge of clock pulse #18.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz) the
maximum possible throughput is approximately 195 kHz and
not the rated 200 kHz.
EXT
DATACLK
CS
R/
C
BUSY
SYNC
DATA
0
t12
t13
t14
1
2
3
4
17
18
t1
t15
t10
t2
t16
t17
t12
t18
t19
BIT 15
(MSB)
BIT 14
BIT 0
(LSB)
Figure 8. Conversion and Read Timing Using an External Continuous Data Clock (EXT/
INT Set to Logic High)
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