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參數(shù)資料
| 型號： | AD9753ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 300MSPS 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 系列： | TxDAC+® |
| 設(shè)置時間： | 11ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 165mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 300M |
| 配用： | AD9753-EB-ND - BOARD EVAL FOR AD9753 |
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REV. B
–14–
AD9753
Substituting the values of IOUTA, IOUTB, and IREF, VDIFF can be
expressed as
VDIFF = {(2 DAC CODE – 4095)/4096}
×
(32 RLOAD/RSET)
× V
REFIO
(8)
These last two equations highlight some of the advantages of
operating the AD9753 differentially. First, the differential opera-
tion will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion, and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (VDIFF) of the
AD9753 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relation-
ship, as shown in Equation 8.
ANALOG OUTPUTS
The AD9753 produces two complementary current outputs,
IOUTA and IOUTB, that may be configured for single-ended or
differential operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, VOUTA and VOUTB,
via a load resistor, RLOAD, as described by Equations 5 through
8 in the DAC Transfer Function section. The differential voltage,
VDIFF, existing between VOUTA and VOUTB, can also be con-
verted to a single-ended voltage via a transformer or differential
amplifier configuration. The ac performance of the AD9753 is
optimum and specified using a differential transformer-coupled
output in which the voltage swing at IOUTA and IOUTB is limited
to
±0.5 V. If a single-ended unipolar output is desirable, IOUTA
should be selected as the output, with IOUTB grounded.
The distortion and noise performance of the AD9753 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can be
significantly reduced by the common-mode rejection of a trans-
former or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more significant
as the frequency content of the reconstructed waveform increases.
This is due to the first order cancellation of various dynamic
common-mode distortion mechanisms, digital feedthrough,
and noise.
Performing a differential-to-single-ended conversion via a trans-
former also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of IOUTA and IOUTB are complemen-
tary, they become additive when processed differentially. A
properly selected transformer will allow the AD9753 to provide
the required power and voltage levels to different loads. Refer to
the Applying the AD9753 Output Configurations section for
examples of various output configurations.
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100 k
in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., VOUTA and VOUTB) due to the nature of a PMOS device.
As a result, maintaining IOUTA and/or IOUTB at a virtual ground
via an I–V op amp configuration will result in the optimum dc
linearity. Note that the INL/DNL specifications for the AD9753
are measured with IOUTA and IOUTB maintained at virtual ground
via an op amp.
IOUTA and IOUTB also have a negative and positive voltage com-
pliance range that must be adhered to in order to achieve optimum
performance. The negative output compliance range of –1.0 V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage and affect the reliability of the AD9753.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS
= 2 mA. The optimum distortion performance for a single-
ended or differential output is achieved when the maximum
full-scale signal at IOUTA and IOUTB does not exceed 0.5 V.
Applications requiring the AD9753’s output (i.e., VOUTA and/
or VOUTB) to extend its output compliance range should size
RLOAD accordingly. Operation beyond this compliance range
will adversely affect the AD9753’s linearity performance and
subsequently degrade its distortion performance.
DIGITAL INPUTS
The AD9753’s digital inputs consist of two channels of 14 data
input pins each and a pair of differential clock input pins. The
12-bit parallel data inputs follow standard straight binary coding
where DB13 is the most significant bit (MSB) and DB0 is the
least significant bit (LSB). IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a
complementary output with the full-scale current split between
the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. With the PLL active or disabled, the DAC
output is updated twice for every input latch rising edge, as
shown in Figures 7 and 11. The AD9753 is designed to support
an input data rate as high as 150 MSPS, giving a DAC output
update rate of 300 MSPS. The setup-and-hold times can also
be varied within the clock cycle as long as the specified mini-
mum times are met. Best performance is typically achieved
when the input data transitions on the falling edge of a 50%
duty cycle clock.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDD) or
VTHRESHOLD = DVDD/2 (
±20%)
The internal digital circuitry of the AD9753 is capable of oper-
ating over a digital supply range of 3.0 V to 3.6 V. As a result,
the digital inputs can also accommodate TTL levels when DVDD
is set to accommodate the maximum high level voltage of the
TTL drivers VOH(max). A DVDD of 3.0 V to 3.6 V typically
ensures proper compatibility with most TTL logic families.
Figure 14 shows the equivalent digital input circuit for the data
and clock inputs.
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| AD9753ASTZRL | 功能描述:IC DAC 12BIT 300MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9753-EB | 功能描述:BOARD EVAL FOR AD9753 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9754 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9754AR | 功能描述:IC DAC 14BIT 125MSPS HP 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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