T
參數(shù)資料
型號: AD9754ARUZ
廠商: Analog Devices Inc
文件頁數(shù): 12/24頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 125MSPS 28-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 50
系列: TxDAC®
設(shè)置時(shí)間: 35ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 220mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 125M
產(chǎn)品目錄頁面: 785 (CN2011-ZH PDF)
DC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
RESOLUTION
14
Bits
DC ACCURACY
1
Integral Linearity Error (INL)
TA = +25
°C
–3.0
±1.5
+3.0
LSB
Differential Nonlinearity (DNL)
TA = +25
°C
–2.0
±0.75
+2.0
LSB
ANALOG OUTPUT
Offset Error
–0.02
+0.02
% of FSR
Gain Error (Without Internal Reference)
–2
±0.5
+2
% of FSR
Gain Error (With Internal Reference)
–5
±1.5
+5
% of FSR
Full-Scale Output Current2
2.0
20.0
mA
Output Compliance Range
–1.0
1.25
V
Output Resistance
100
k
Output Capacitance
5
pF
REFERENCE OUTPUT
Reference Voltage
1.14
1.20
1.26
V
Reference Output Current3
100
nA
REFERENCE INPUT
Input Compliance Range
0.1
1.25
V
Reference Input Resistance
1
M
Small Signal Bandwidth
0.5
MHz
TEMPERATURE COEFFICIENTS
Offset Drift
0
ppm of FSR/
°C
Gain Drift (Without Internal Reference)
±50
ppm of FSR/
°C
Gain Drift (With Internal Reference)
±100
ppm of FSR/
°C
Reference Voltage Drift
±50
ppm/
°C
POWER SUPPLY
Supply Voltages
AVDD
4.5
5.0
5.5
V
DVDD
2.7
5.0
5.5
V
Analog Supply Current (IAVDD)
4
34
39
mA
Digital Supply Current (IDVDD)
5
3.0
5
mA
Supply Current Sleep Mode (IAVDD)
6
4.0
8
mA
Power Dissipation5 (5 V, IOUTFS = 20 mA)
185
220
mW
Power Supply Rejection Ratio7—AVDD
–0.4
+0.4
% of FSR/V
Power Supply Rejection Ratio7—DVDD
–0.025
+0.025
% of FSR/V
OPERATING RANGE
–40
+85
°C
NOTES
1Measured at IOUTA, driving a virtual ground.
2Nominal full-scale current, I
OUTFS, is 32
× the I
REF current.
3Use an external buffer amplifier to drive any external load.
4Requires +5 V supply.
5Measured at f
CLOCK = 25 MSPS and IOUT = static full scale (20 mA).
6Logic level for SLEEP pin must be referenced to AVDD. Min V
IH = 3.5 V.
7
± 5% Power supply variation.
Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
–2–
REV. A
AD9754–SPECIFICATIONS
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