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參數(shù)資料
| 型號： | AD9764ARU |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 125MSPS 28-TSSOP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 50 |
| 系列： | TxDAC® |
| 設置時間： | 35ns |
| 位數(shù)： | 14 |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 170mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 125M |
REV. B
AD9764
–9–
FUNCTIONAL DESCRIPTION
Figure 21 shows a simplified block diagram of the AD9764. The
AD9764 consists of a large PMOS current source array that is
capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 k
).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS differen-
tial current switches. The switches are based on a new architec-
ture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the dif-
ferential current switches.
The analog and digital sections of the AD9764 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, RSET. The external resistor, in combination with
both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is mirrored over to
the segmented current sources with the proper scaling factor.
The full-scale current, IOUTFS, is 32 times the value of IREF.
DAC TRANSFER FUNCTION
The AD9764 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 16383) while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/16384)
× I
OUTFS
(1)
IOUTB = (16383 – DAC CODE)/16384
× I
OUTFS
(2)
where DAC CODE = 0 to 16383 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage
VREFIO and external resistor RSET. It can be expressed as:
IOUTFS = 32
× I
REF
(3)
where IREF = VREFIO/RSET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note
that RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50
or 75 cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply:
VOUTA = IOUTA
× R
LOAD
(5)
VOUTB = IOUTB
× R
LOAD
(6)
Note that the full-scale value of VOUTA and VOUTB should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, VDIFF, appearing across IOUTA and
IOUTB is:
VDIFF = (IOUTA – IOUTB)
× R
LOAD
(7)
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be
expressed as:
VDIFF = {(2 DAC CODE – 16383)/16384}
×
VDIFF = {(32 RLOAD/RSET)
× V
REFIO
(8)
These last two equations highlight some of the advantages of
operating the AD9764 differentially. First, the differential op-
eration will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (VDIFF) of the
AD9764 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relation-
ship as shown in Equation 8.
DIGITAL DATA INPUTS (DB13–DB0)
50pF
COMP1
+1.20V REF
AVDD
ACOM
REFLO
COMP2
PMOS
CURRENT SOURCE
ARRAY
0.1 F
+5V
SEGMENTED SWITCHES
FOR DB13–DB5
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
RSET
2k
0.1 F
IOUTA
IOUTB
0.1 F
AD9764
SLEEP
IREF
VREFIO
CLOCK
IOUTB
IOUTA
RLOAD
50
VOUTB
VOUTA
RLOAD
50
VDIFF = VOUTA – VOUTB
LATCHES
Figure 21. Functional Block Diagram
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