參數(shù)資料
型號(hào): AD976ARRL
廠商: Analog Devices Inc
文件頁數(shù): 5/16頁
文件大小: 0K
描述: IC ADC 16BIT 100KSPS 28-SOIC
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 16
采樣率(每秒): 200k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 100mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,雙極
配用: EVAL-AD976CB-ND - BOARD EVAL FOR AD976
EVAL-AD976ACB-ND - BOARD EVAL FOR AD976A
AD976/AD976A
–13–
REV. C
DC CODE UNCERTAINTY
Ideally, a fixed dc input should result in the same output code
for repetitive conversions; however, as a consequence of un-
avoidable circuit noise within the wideband circuits of the ADC,
a range of output codes may occur for a given input voltage.
Thus, when a dc signal is applied to the AD976/AD976A input,
and 10,000 conversions are recorded, the result will be a distri-
bution of codes as shown in Figure 19. This histogram shows a
bell-shaped curve consistent with the Gaussian nature of ther-
mal noise. The histogram is approximately seven codes wide.
The standard deviation of this Gaussian distribution results in a
code transition noise of 1 LSB rms.
4000
3500
0
–3
2000
1500
1000
500
3000
2500
–2
–1
0
1
2
3
4
Figure 19. Histogram of 10,000 Conversions of a DC Input
MICROPROCESSOR INTERFACING
The AD976/AD976A is ideally suited for traditional dc mea-
surement applications supporting a microprocessor and ac signal
processing applications interfacing to a digital signal processor.
The AD976/AD976A is designed to interface with a 16-bit data
bus and provides all output data bits in a single read cycle. A
variety of external buffers can be used with the AD976/AD976A
to prevent bus noise from coupling into the ADC. The following
sections illustrate the use of the AD976/AD976A with the
MC68000 and 8051 microcontrollers and the TMS320C25 and
ADSP-2111 signal processors.
MC68000 Interface
Figure 20 shows a general interface diagram for the MC68000
16-bit microprocessor to the AD976/AD976A. In Figure 20,
conversion is initiated by bringing CSA low (i.e., writing to the
appropriate address). This allows the processor to maintain
control over the complete conversion process.
ADDRESS BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
DB15
DB0
BUSY
AD976/
AD976A
R/
C
BUS
74HC374
OE
Q15
Q0
D0
D15
CLK
EN
ADDR
DECODE
A0
A15
D15
D0
68000
R/W
AS
Figure 20. AD976/AD976A to 68000 Interface
250
0
150
100
200
50
NUMBER
OF
UNITS
0
0.2
0.3
0.4
0.6
0.7
0.8
1.0
1.1
1.2
1.4
1.5
1.6
1.8
1.9
2.0
2.2
2.3
2.4
2.6
2.7
2.8
3.0
3.1
3.2
POSITIVE DNL DISTRIBUTION – LSB
Figure 17. Typical Position DNL Distribution (1516 Units)
140
0
80
20
120
100
NUMBER
OF
UNITS
–1.2
NEGATIVE DNL DISTRIBUTION – LSB
60
40
–1.2
–1.1
–1
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
Figure 18. Typical Negative DNL Distribution (1516 Units)
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