參數(shù)資料
型號: AD976BRZRL
廠商: Analog Devices Inc
文件頁數(shù): 11/16頁
文件大小: 0K
描述: IC ADC 16BIT 100KSPS 28SOIC
標準包裝: 1,000
位數(shù): 16
采樣率(每秒): 100k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 100mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個單端,雙極
配用: EVAL-AD976CB-ND - BOARD EVAL FOR AD976
EVAL-AD976ACB-ND - BOARD EVAL FOR AD976A
AD976/AD976A
–4–
REV. C
All Grades
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL OUTPUTS
Data Format
Parallel 16 Bits
Data Coding
Binary Twos Complement
VOL
ISINK = 1.6 mA
+0.4
V
VOH
ISOURCE = 500 A+4
V
Leakage Current
High-Z State,
±5
A
VOUT = 0 V to VDIG
Output Capacitance
High-Z State
15
pF
DIGITAL TIMING
Bus Access Time
83
ns
Bus Relinquish Time
83
ns
POWER SUPPLIES
Specified Performance
VDIG
4.75
5
5.25
V
VANA
4.75
5
5.25
V
IDIG
3.0
mA
IANA
11
mA
Power Dissipation
100
mW
TEMPERATURE RANGE
Specified Performance
–40
+85
°C
Specifications subject to change without notice.
TIMING SPECIFICATIONS (AD976A: F
S = 200 kHz; AD976: FS = 100 kHz; –40 C to +85 C, VDIG = VANA = +5 V unless otherwise noted)
Symbol
Min
Typ
Max
Units
Convert Pulsewidth
t1
50
ns
Data Valid Delay after R/C Low (AD976A/AD976)
t2
4.0/8.0
s
BUSY Delay from R/C Low
t3
83
ns
BUSY Low (AD976A/AD976)
t4
4.0/8.0
s
BUSY Delay after End of Conversion (AD976A/AD976)
t5
180/360
ns
Aperture Delay
t6
40
ns
Conversion Time (AD976A/AD976)
t7
3.8/7.6
4.0/8.0
s
Acquisition Time
t8
1.0/2.0
s
Bus Relinquish Time
t9
10
35
83
ns
BUSY Delay after Data Valid (AD976A/AD976)
t10
50
180/360
ns
Previous Data Valid after R/C Low (AD976A/AD976)
t11
3.7/7.4
s
Throughput Time (AD976A/AD976)
t7 + t8
5/10
s
R/C to CS Setup Time
t12
10
ns
Time Between Conversions (AD976A/AD976)
t13
5/10
s
Bus Access and Byte Delay
t14
10
83
ns
Specifications subject to change without notice.
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