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| 型號： | AD9776ABSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAC 12BIT 1.0GSPS 100-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 1G |
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AD9776A/AD9778A/AD9779A
Rev. B | Page 37 of 56
INTERPOLATION FILTER BANDWIDTH LIMITS
The AD9776A/AD9778A/AD9779A use a novel interpolation
filter architecture that allows DAC IF frequencies to be gener-
ated anywhere in the spectrum. Figure 68 shows the traditional
choice of DAC IF output bandwidth placement. Note that there
are no possible filter modes in which the carrier can be placed
near 0.5 × fDATA, 1.5 × fDATA, 2.5 × fDATA, and so on.
10
–80
–4
4
fOUT (× Input Data Rate),
ASSUMING 8× INTERPOLATION
AT
T
E
NUAT
IO
N
(
d
B)
0
–10
–20
–30
–40
–50
–60
–70
–3
–2
–1
0123
+f
DAC
/2
+f
DAC
/4
+f
DAC
/8
B
A
SEB
A
N
D
–f
DA
C
/8
–f
DA
C
/4
–f
DA
C
/2
06
45
2-
0
65
Figure 68. Traditional Bandwidth Options for TxDAC Output IF
The filter architecture not only allows the interpolation filter
pass bands to be centered in the middle of the input Nyquist
zones (as explained in this section), but also allows the possi-
bility of a 3 × fDAC/8 modulation mode when interpolating by 8.
With all of these filter combinations, a carrier of given bandwidth
can be placed anywhere in the spectrum and fall into a possible
pass band of the interpolation filters. The possible bandwidths
accessible with the filter architecture are shown in Figure 69 and
Figure 70. Note that the shifted and nonshifted filter modes are
all accessible by programming the filter mode for a particular
interpolation rate.
10
–80
–4
4
fOUT (× Input Data Rate),
ASSUMING 8× INTERPOLATION
AT
T
E
NUAT
IO
N
(
d
B)
0
–10
–20
–30
–40
–50
–60
–70
–3
–2
–1
0
1
2
3
–f
DA
C
/2
–3
×
f DAC
/8
–f
DA
C
/4
–f
DA
C
/8
B
A
SEB
A
N
D
+f
DAC
/8
+f
DAC
/4
+3
×
f DA
C
/8
+f
DAC
/2
06
45
2-
0
66
Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture
10
–80
–4
4
fOUT (× Input Data Rate),
ASSUMING 8× INTERPOLATION
AT
T
E
N
U
AT
IO
N
(
d
B
)
0
–10
–20
–30
–40
–50
–60
–70
–3
–2
–1
0123
S
H
IF
T
E
D
–3
×
f DAC
/8
SH
IF
T
ED
–
f DA
C
/4
SH
IF
T
ED
–
f DA
C
/8
SH
IF
T
ED
–
D
C
SH
IF
T
ED
+
D
C
SH
IF
T
ED
+
f DA
C
/8
SH
IF
T
ED
+
f DA
C
/4
SH
IF
T
ED
+
3
×
f DA
C
/8
06
45
2-
08
7
Figure 70. Shifted Bandwidths Accessible with the Filter Architecture
With this filter architecture, a signal placed anywhere in the
spectrum is possible. However, the signal bandwidth is limited
by the input sample rate of the DAC and the specific placement
of the carrier in the spectrum. The bandwidth restriction resulting
from the combination of filter response and input sample rate is
often referred to as the synthesis bandwidth, because this is the
largest bandwidth that the DAC can synthesize.
The maximum bandwidth condition exists if the carrier is
placed directly in the center of one of the filter pass bands. In
this case, the total 0.1 dB bandwidth of the interpolation filters
width as a fraction of the DAC output sample rate drops by a
factor of 2 for every doubling of interpolation rate. The mini-
mum bandwidth condition exists, for example, if a carrier is
placed at 0.25 × fDATA. In this situation, if the nonshifted filter
response is enabled, the high end of the filter response cuts off
at 0.4 × fDATA, thus limiting the high end of the signal bandwidth.
If the shifted filter response is instead enabled, then the low end
of the filter response cuts off at 0.1 × fDATA, thus limiting the low
end of the signal bandwidth. The minimum bandwidth speci-
fication that applies for a carrier at 0.25 × fDATA is therefore 0.3 ×
fDATA. The minimum bandwidth behavior is repeated over the
spectrum for carriers placed at (±n ± 0.25) × fDATA, where n is
any integer.
Digital Modulation
The digital quadrature modulation occurs within the interpolation
filter. The modulation shifts the frequency spectrum of the
incoming data by the frequency offset selected. The frequency
offsets available are multiples of the input data rate. The
modulation is equivalent to multiplying the quadrature input
signal by a complex carrier signal, C(t), of the following form:
C(t) = cos(ωct) + j sin(ωct)
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| AD9776A-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9776A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9776A-EBZ | 制造商:Analog Devices 功能描述:Dual 12 /14 /16 Bit, 1 GSPS, Digital To Analog Converters Development Kit 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk |
| AD9776BSVZ | 功能描述:IC DAC 12BIT DUAL 1GSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9776BSVZRL | 功能描述:IC DAC 12BIT DUAL 1GSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9776-EB | 制造商:Analog Devices 功能描述:AD9776 EVAL BOARD - Bulk |
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