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參數(shù)資料
| 型號： | AD977ACRSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 200KSPS 28SSOP |
| 標準包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 3 個單端，單極；3 個單端，雙極 |
| 配用： | EVAL-AD977CB-ND - BOARD EVAL FOR AD977 EVAL-AD977ACB-ND - BOARD EVAL FOR AD977A |
AD977/AD977A
–6–
REV. D
PIN FUNCTION DESCRIPTIONS
Pin No.
DIP/SOIC
SSOP
Mnemonic
Description
1, 3, 4
R1IN, R2IN, R3IN
Analog Input. Refer to Table I, Table II for input range configuration.
2
AGND1
Analog Ground. Used as the ground reference point for the REF pin.
5
6
CAP
Reference buffer output. Connect a 2.2
F tantalum capacitor between CAP and
Analog Ground.
6
7
REF
Reference Input/Output. The internal 2.5 V reference is available at this pin.
Alternatively an external reference can be used to override the internal reference. In
either case, connect a 2.2
F tantalum capacitor between REF and Analog Ground.
7
9
AGND2
Analog Ground.
8
12
SB/
BTC
This digital input is used to select the data format of a conversion result. With SB/
BTC
tied LOW, conversion data will be output in Binary Two’s Complement format. With
SB/
BTC connected to a logic HIGH, data is output in Straight Binary format.
9
13
EXT/
INT
Digital select input for choosing the internal or an external data clock. With EXT/
INT
tied LOW, after initiating a conversion, 16 DATACLK pulses transmit the previous
conversion result as shown in Figure 3. With EXT/
INT set to a logic HIGH, output
data is synchronized to an external clock signal connected to the DATACLK input.
Data is output as indicated in Figure 4 through Figure 9.
10
14
DGND
Digital Ground.
11
15
SYNC
Digital output frame synchronization for use with an external data clock
(EXT/
INT = Logic HIGH). When a read sequence is initiated, a pulse one
DATACLK period wide is output synchronous to the external data clock.
12
16
DATACLK
Serial data clock input or output, dependent upon the logic state of the EXT/
INT
pin. When using the internal data clock (EXT/
INT = Logic LOW), a conversion
start sequence will initiate transmission of 16 DATACLK periods. Output data is
synchronous to this clock and is valid on both its rising and falling edges (Figure 3).
When using an external data clock (EXT/
INT = Logic HIGH), the CS and R/C
signals control how conversion data is accessed.
13
17
DATA
The serial data output is synchronized to DATACLK. Conversion results are
stored in an on-chip register. The AD977 provides the conversion result, MSB first,
from its internal shift register. The DATA format is determined by the logic level of
SB/
BTC. When using the internal data clock (EXT/INT = Logic LOW), DATA is
valid on both the rising and falling edges of DATACLK. Between conversions
DATA will remain at the level of the TAG input when the conversion was started.
Using an external data clock (EXT/
INT = Logic HIGH) allows previous conversion
data to be accessed during a conversion (Figures 5, 7 and 9) or the conversion
result can be accessed after the completion of a conversion (Figures 4, 6 and 8).
14
19
TAG
This digital input can be used with an external data clock, (EXT/
INT = Logic
HIGH) to daisy chain the conversion results from two or more AD977s onto a
single DATA line. The digital data level on TAG is output on DATA with a delay
of 16 or 17 external DATACLK periods after the initiation of the read sequence.
Dependent on whether a SYNC is not present or present.
15
21
R/
C
Read/Convert Input. Is used to control the conversion and read modes of the
AD977. With
CS LOW; a falling edge on R/C holds the analog input signal inter-
nally and starts a conversion, a rising edge enables the transmission of the conver-
sion result.
16
24
CS
Chip Select Input. With R/
C LOW, a falling edge on CS will initiate a conversion.
With R/
C HIGH, a falling edge on CS will enable the serial data output sequence.
17
25
BUSY
Busy Output. Goes LOW when a conversion is started, and remains LOW until the
conversion is completed and the data is latched into the on-chip shift register.
18
26
PWRD
Power-Down Input. When set to a logic HIGH power consumption is reduced and
conversions are inhibited. The conversion result from the previous conversion is
stored in the onboard shift register.
19
27
VANA
Analog Power Supply. Nominally 5 V.
20
28
VDIG
Digital Power Supply. Nominally 5 V.
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