參數(shù)資料
型號(hào)： AD9787-DPG2-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/64頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9787
標(biāo)準(zhǔn)包裝： 1
系列： *
DAC 的數(shù)量： 2
位數(shù)： 14
采樣率（每秒）： 800M
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 22ms
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9787
AD9785/AD9787/AD9788
Rev. A | Page 27 of 64
The data synchronization control register (DSCR) comprises two bytes located at Address 0x02.
Table 12. Data Synchronization Control Register (DSCR)
Address
Bit
Name
Description
0x02
[15:11]
DATACLK Delay [4:0]
Controls the amount of delay applied to the output data clock signal. The minimum delay
corresponds to the 00000 state, and the maximum delay corresponds to the 11111 state.
The minimum delay is 0.7 ns and the maximum delay is 6.5 ns. The incremental delay is
190 ps and corresponds to an incremental change in the data clock delay bits.
[10:7]
Data Timing Margin [3:0]
The data timing margin bits control the amount of delay applied to the data and clock
signals used for checking setup and hold times, respectively, on the input data ports, with
respect to the internal data assembler clock. The minimum delay corresponds to the 0000
state, and the maximum delay corresponds to the 1111 state. The delays are 190 ps.
[6]
LVDS data clock enable
0: Default. When the LVDS data clock enable bit is cleared, the SYNC_O+ and SYNC_O
LVDS pad cells are driven by the multichip synchronization logic.
1: When the LVDS data clock enable bit is set, the SYNC_O+ and SYNC_O LVDS pad cells
are driven by the signal that drives the CMOS DATACLK output pad.
[5]
DATACLK invert
0: Default. When the data clock invert bit is cleared, the DATACLK signal is in phase with
the clock that samples the data into the part.
1: When the DATACLK invert bit is set, the DATACLK signal is inverted from the clock that
samples the data into the part.
[4]
DATACLK delay enable
0: Default. When the DATACLK delay enable bit is cleared, the data port input
synchronization function is effectively inactive and the delay is bypassed.
1: When the DATACLK delay enable bit is set, the data port input synchronization function
is active and controlled by the data delay mode bits. The data output clock is routed
through the delay cell.
[3]
Data timing mode
Determines the timing optimization mode. See the Optimizing the Data Input Timing
section for details.
0: Manual timing optimization mode
1: Automatic timing optimization mode
[2]
Set high
This bit should always be set high.
[1]
Data sync polarity
0: Default. The digital input data sampling edge is aligned with the falling edge of DCI.
1: The digital input data sampling edge is aligned with the rising edge of DCI.
Used only in slave mode (see the MSCR register, Address 0x03, Bit 16).
[0]
Reserved
Reserved for future use.
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