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參數(shù)資料
| 型號： | AD9878BSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Mixed-Signal Front End for Broadband Applications |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, MS-026BED, LQFP-100 |
| 文件頁數(shù)： | 1/36頁 |
| 文件大?。?/td> | 749K |
| 代理商： | AD9878BSTZ |
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Mixed-Signal Front End
for Broadband Applications
AD9878
FEATURES
Rev.
A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Tel: 781.329.4700Fax: 781.326.8703
Low cost 3.3 V CMOS MxFE for broadband applications DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+)
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
Analog Tx output level adjust
Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input
10-bit, 29 MSPS sampling ADC
8-bit ∑- auxiliary DAC
Direct interface to AD832x family of PGA cable drivers
APPLICATIONS
Cable set-top boxes
Cable and wireless modems
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
0
–
I
Q
12
TxID[5:0]
Σ
-
OUTPUT
CA PORT
MCLK
OSCIN
IF10 INPUT
IF12B INPUT
VIDEO IN
IF12A INPUT
CLAMP
LEVEL
Tx
SDIO
IF10[4:0]
IF12[11:0]
FLAG[2:1]
Tx
16
DDS
SINC
–1
Σ
-
4
10
3
12
12
MUX
ADC
ADC
ADC
MUX
MUX
MUX
DAC
Σ
CONTROL REGISTERS
PLL
Figure 1.
The AD9878 is a single-supply, cable modem/set-top box,
mixed-signal front end. The device contains a transmit path
interpolation filter, a complete quadrature digital upconverter,
and a transmit DAC. The receive path contains dual 12-bit
ADCs and a 10-bit ADC. All internally required clocks and an
output system clock are generated by the phase-locked loop
(PLL) from a single crystal oscillator or clock input.
The transmit path interpolation filter provides an upsampling
factor of 16× with an output signal bandwidth up to 4.35 MHz.
Carrier frequencies up to 65 MHz with 26 bits of frequency tuning
resolution can be generated by the direct digital synthesizer
(DDS). The transmit DAC resolution is 12 bits and can run at
sampling rates as high as 232 MSPS. Analog output scaling from
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
The 12-bit ADCs provide excellent undersampling performance,
allowing this device to typically deliver better than 10 ENOBs
with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at
rates up to 29 MHz, allowing them to process wideband signals.
The AD9878 includes a programmable ∑- DAC, which can be
used to control an external component such as a variable gain
amplifier (VGA) or a voltage controlled tuner.
The AD9878 also integrates a CA port that enables a host
processor to interface with the AD832x family of programmable
gain amplifier (PGA) cable drivers or industry equivalent via
the MxFE serial port (SPORT).
The AD9878 is available in a 100-lead, LQFP package. The
AD9878 is specified over the extended industrial (40°C to
+85°C) temperature range.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9878-EB | 制造商:Analog Devices 功能描述:EVAL KIT FOR MIXED-SGNL FRONT END FOR BROADBAND APPLICATIONS - Bulk |
| AD9879 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front End Set-Top Box, Cable Modem |
| AD9879_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front End Set-Top Box, Cable Modem |
| AD9879BS | 制造商:Analog Devices 功能描述: |
| AD9879BSZ | 功能描述:IC PROCESSOR FRONT END 100MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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