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參數(shù)資料
| 型號： | AD9883ABSTZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE FLAT 140MHZ 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 顯示器，監(jiān)控器，電視 |
| 接口： | 模擬 |
| 電源電壓： | 3 V ~ 3.6 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. B
AD9883A
–21–
13
7–0 Post-Coast
This register allows the coast signal to be applied follow-
ing the Vsync signal. This is necessary in cases where
post-equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
14
7 Hsync Detect
This bit is used to indicate when activity is detected on
the Hsync input pin (Pin 30). If Hsync is held high or
low, activity will not be detected.
Table XXVII. Hsync Detection Results
Detect
Function
0No Activity Detected
1Activity Detected
The sync processing block diagram shows where this
function is implemented.
14
6 AHS – Active Hsync
This bit indicates which Hsync input source is being used
by the PLL (Hsync input or Sync-on-Green). Bits 7 and 1
in this register determine which source is used. If both
Hsync and SOG are detected, the user can determine which
has priority via Bit 3 in register 0EH. The user can override
this function via Bit 4 in register 0EH. If the override bit
is set to Logic 1, then this bit will be forced to whatever
the state of Bit 3 in register 0EH is set to.
Table XXVIII. Active Hsync Results
Bit 7
Bit 1
Bit 4,
(Hsync
(SOG
Reg 0EH
Detect)
(Override)
AHS
00
0
Bit 3 in 0EH
01
0
1
10
0
11
0
Bit 3 in 0EH
XX
1
Bit 3 in 0EH
AHS = 0 means use the Hsync pin input for Hsync.
AHS = 1 means use the SOG pin input for Hsync.
The override bit is in register 0EH, Bit 4.
14
5 Detected Hsync Input Polarity Status
This bit reports the status of the Hsync input polarity
detection circuit. It can be used to determine the polarity
of the Hsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 12).
Table XXIX. Detected Hsync Input Polarity Status
Hsync Polarity Status
Result
0Negative
1
Positive
14
4 Vsync Detect
This bit is used to indicate when activity is detected on
the Vsync input pin (Pin 31). If Vsync is held steady high
or low, activity will not be detected.
Table XXX. Vsync Detection Results
Detect
Function
0No Activity Detected
1Activity Detected
The Sync Processing Block Diagram (Figure 12) shows
where this function is implemented.
14
3 AVS – Active Vsync
This bit indicates which Vsync source is being used: the
Vsync input or output from the sync separator. Bit 4 in this
register determines which is active. If both Vsync and
SOG are detected, the user can determine which has
priority via Bit 0 in register 0EH. The user can override this
function via Bit 1 in register 0EH. If the override bit is set
to Logic 1, this bit will be forced to whatever the state of Bit 0
in register 0EH is set.
Table XXXI. Active Vsync Results
AVS = 0 means Vsync input.
AVS = 1 means Sync separator.
The override bit is in register 0EH, Bit 1.
14
2
Detected Vsync Output Polarity Status
This bit reports the status of the Vsync output polarity
detection circuit. It can be used to determine the polarity
of the Vsync output. The detection circuit’s location is-
shown in the Sync Processing Block Diagram (Figure 12).
Table XXXII. Detected Vsync Output Polarity Status
Vsync Polarity Status
Result
0Active Low
1Active High
14
1
Sync-on-Green Detect
This bit is used to indicate when sync activity is detected
on the Sync-on-Green input pin (Pin 49).
Table XXXIII. Sync-on-Green Detection Results
Detect
Function
0No Activity Detected
1Activity Detected
The Sync Processing Block Diagram (Figure 12) shows
where this function is implemented.
14
0
Detected Coast Polarity Status
This bit reports the status of the Coast input polarity
detection circuit. It can be used to determine the polarity
of the Coast input. The detection circuit’s location is shown
in the Sync Processing Block Diagram (Figure 12).
Bit 4, Reg 14H
Bit 1, Reg 0EH
(Vsync Detect)
(Override)
AVS
10
0
00
1
X1
Bit 0 in 0EH
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