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AD9888
Data Sheet
Rev. C | Page 4 of 36
SPECIFICATIONS
VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate.
Table 1.
AD9888KSZ-170
Parameter
Temp
Test
Level
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
8
Bits
DC ACCURACY
Differential Nonlinearity
25°C
I
±0.5
±1.25/1.0
±0.6
+1.25/1.0
LSB
Full
VI
+1.35/1.0
+1.50/1.0
LSB
Integral Nonlinearity
25°C
I
±0.5
±2.0
±0.75
±2.25
LSB
Full
VI
±2.5
±2.75
LSB
No Missing Codes
25°C
I
Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum
25°C
I
0.5
V p-p
Maximum
25°C
I
1.0
V p-p
Gain Temperature Coefficient
25°C
V
100
ppm/°C
Input Bias Current
25°C
IV
1
μA
Full
IV
2
μA
Input Capacitance
Full
V
3
pF
Input Resistance
Full
IV
1
M
Input Offset Voltage
Full
VI
7
90
7
90
mV
Input Full-Scale Matching
Full
VI
2.5
9.0
2.5
9.0
% FS
Offset Adjustment Range
Full
VI
44
49
53
44
49
53
% FS
REFERENCE OUTPUT
Output Voltage
Full
VI
1.20
1.25
1.30
1.20
1.25
1.30
V
Temperature Coefficient
Full
V
±50
ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate
Full
VI
100/140
170
MSPS
Minimum Conversion Rate
Full
IV
10
MSPS
Clock to Data Skew (tskew)
Full
IV
1.25
+1.25
1.25
+1.25
ns
tBUFF
Full
VI
4.7
μs
tSTAH
Full
VI
4.0
μs
tDHO
Full
VI
250
ns
tDAL
Full
VI
4.7
μs
tDAH
Full
VI
4.0
μs
tDSU
Full
VI
250
ns
tSTASU
Full
VI
4.7
μs
tSTOSU
Full
VI
4.0
μs
HSYNC Input Frequency
Full
IV
15
110
15
110
kHz
Maximum PLL Clock Rate
Full
VI
100/140
170
MHz
Minimum PLL Clock Rate
Full
IV
10
MHz
25°C
IV
470
700
450
700
ps p-p
Full
IV
1000
ps p-p
Sampling Phase Temperature
Coefficient
Full
IV
15
ps/°C