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參數(shù)資料
| 型號(hào)： | AD9901KPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PHS/FREQ DISCRIMINATOR 20PLCC |
| 標(biāo)準(zhǔn)包裝： | 49 |
| 類型： | 數(shù)字相位/頻率鑒別器 |
| PLL： | 是 |
| 輸入： | CMOS，ECL，TTL |
| 輸出： | CMOS，ECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 5V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 551 (CN2011-ZH PDF) |
AD9901
REV. B
–7–
10
0%
100
90
500mV
200ns
Figure 8. AD9901 Output Waveform
(FO << FI)
It is important to note that the slope of the transfer function is
constant near its midpoint. Many digital phase comparators have
an area near the lock point where their gain goes to zero, result-
ing in a “dead zone.” This causes increased phase noise (jitter) at
the lock point.
The AD9901 avoids this dead zone by shifting it to the end-
points of the transfer curve, as indicated in Figure 7. The in-
creased gain at either end increases the effective error signal to
pull the oscillator back into the linear region. This does not
affect phase noise, which is far more dependent upon lock region
characteristics.
It should be noted, however, that as frequency increases, the
linear range is decreased. At the ends of the detection range, the
reference and oscillator inputs approach phase alignment. At this
point, slew rate limiting in the detector effectively increases
phase gain. This decreases the linear detection by nominally
3.6 ns. Therefore, the typical detection range can be found by
calculating [(1/F – 3.6 ns)/(1/F)]
× 360°. As an example, at
200 MHz the linear phase detection range is
±50°.
Away from lock, the AD9901 becomes a frequency discrimina-
tor. Any time either the reference or oscillator input occurs twice
before the other, the Frequency High or Frequency Low flip-flop
is clocked to logic LOW. This overrides the XOR output and
holds the output at the appropriate level to pull the oscillator
toward the reference frequency. Once the frequencies are within
the linear range, the phase detector circuit takes over again.
Combining the frequency discriminator with the phase detector
eliminates locking to a harmonic of the reference.
Figure 8 shows the effect of the “Frequency Low” flip-flop when
the oscillator frequency is much lower than the reference input.
The narrow pulses, which result from cycles when two positive
reference-input transitions occur before a positive VCO edge,
increase the dc mean value. Figure 9 illustrates the inverse effect
when the “Frequency High” flip-flop reacts to a much higher
VCO frequency.
Figure 10 shows the output waveform at lock for 50 MHz opera-
tion. This output results when the phase difference between
reference and oscillator is approximately –
πRad.
AD9901 APPLICATIONS
The figure below illustrates a phase-locked loop (PLL) system
utilizing the AD9901. The first step in designing this type of
circuit is to characterize the VCO’s output frequency as a func-
tion of tuning voltage. The transfer function of the oscillator in
the diagram is shown in Figure 11.
10
0%
100
90
500mV
200ns
Figure 9. AD9901 Output Waveform
(FO >> FI)
10
0%
100
90
500mV
5ns
Figure 10. AD9901 Output Waveform
(FO = FI = 50 MHz)
VARACTORS TUNING VOLTAGE – Volts
165
–1
FREQUENCY
–
MHz
155
145
135
125
115
105
95
85
75
65
0
12
3
4
5
6
Figure 11. VCO Frequency vs. Voltage
Next, the range of frequencies over which the VCO is to operate
is examined to assure that it lies on a linear portion of the transfer
curve. In this case, frequencies from 100 MHz to 120 MHz
result from tuning voltages of approximately +1.5 V to +2.5 V.
Because the nominal output swing of the AD9901 is 0 V to –1.8 V,
an inverting amplifier with a gain of 2 follows the loop filter.
As shown in the illustration, a simple passive RC low-pass filter
made up of two resistors and a tantalum capacitor eliminates the
need for an expensive high speed op amp active-filter design. In
this passive-filter second-order-loop system, where n = 2, the
damping factor is equal to:
δ = 0.5 [K
OK d /n(τ1 + τ2)]
1/2 [
τ
2 + (n/KOKd)]
and the values for
τ
1 and τ2 are the low-pass filter’s time con-
stants R1C and R2C. The gain of 2 of the inverting stage, when
combined with the phase detector’s gain, gives:
Kd = 0.572 V/RAD
With KO = 115.2 MRAD/s/V, τ1 equals 1.715s, and τ2 equals
3.11
× 10–4s for the required damping factor of 0.7. The illus-
trated values of 30
(R1), 160 (R2), and 10 F (C) in the
diagram approximate these time constants.
The gain of the RC filter is:
VO/VI = (1 + sR2C)/[1 + s(R1 + R2)C].
Where KOKd >> ωn, the system’s natural frequency:
ω
n = [KOK d/n(τ1 + τ2)]
1/2 = 4.5 kHz.
For general information about phase-locked loop design, the
user is advised to consult the following references: Gardner,
Phase-Lock Techniques (Wiley); or Best, Phase Locked Loops
(McGraw-Hill).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9901KPZ | 制造商:Analog Devices 功能描述:IC DISCRIMINATOR ((NW)) |
| AD9901KPZ-REEL | 功能描述:IC DISCRIMINATOR PH/FREQ 20PLCC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9901KQ | 功能描述:IC PHASE/FREQ DISCRIMR 14-CDIP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9901TE/883 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrahigh Speed Phase/Frequency Discriminator |
| AD9901TQ/883 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrahigh Speed Phase/Frequency Discriminator |
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