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參數(shù)資料
| 型號： | AD9985AKSTZ-110 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE 8BIT 110MSPS 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | 視頻 |
| 接口： | 串行 |
| 電源電壓： | 2.2 V ~ 3.45 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9985
Rev. 0 | Page 14 of 32
FREQUENCY (MHz)
14
12
0
P
IX
E
L
CLO
CK
J
ITTE
R
(p-p)
(%)
10
8
6
4
2
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
04799-0-007
Figure 7. Pixel Clock Jitter vs. Frequency
The PLL characteristics are determined by the loop filter design,
by the PLL charge pump current, and by the VCO range setting.
The loop filter design is illustrated in Figure 8. Recommended
settings of VCO range and charge pump current for VESA
standard display modes are listed in Table 9.
CP
0.0082
F
CZ
0.082
F
RZ
2.7k
FILT
PVD
04799-0-008
Figure 8. PLL Loop Filter Detail
Four programmable registers are provided to optimize the
performance of the PLL:
1.
The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock
frequencies in the range of 12 MHz to 110 MHz. The
Divisor register controls the exact multiplication factor.
This register may be set to any value between 221 and 4095.
(The divide ratio that is actually used is the programmed
divide ratio plus one.)
2.
The 2-Bit VCO Range Register. To improve the noise
performance of the AD9985, the VCO operating frequency
range is divided into three overlapping regions. The VCO
range register sets this operating range. Table 6 lists the
frequency ranges for the lowest and highest regions.
Table 6. VCO Frequency Ranges
Pixel Clock Range (MHz)
PV1
PV0
AD9985KSTZ
AD9985BSTZ
0
12–32
12–30
0
1
32–64
30–60
1
0
64–110
60–110
1
110–140
3.
The 3-Bit Charge Pump Current Register. This register
allows the current that drives the low-pass loop filter to be
varied. The possible current values are listed in Table 7.
Table 7. Charge Pump Current/Control Bits
Ip2
Ip1
Ip0
Current (A)
0
50
0
1
100
0
1
0
150
0
1
250
1
0
350
1
0
1
500
1
0
750
1
1500
4.
The 5-Bit Phase Adjust Register. The phase of the gen-
erated sampling clock may be shifted to locate an optimum
sampling point within a clock cycle. The phase adjust
register provides 32 phase-shift steps of 11.25° each. The
Hsync signal with an identical phase shift is available
through the HSOUT pin.
The COAST pin is used to allow the PLL to continue to
run at the same frequency, in the absence of the incoming
Hsync signal or during disturbances in Hsync (such as
equalization pulses). This may be used during the vertical
sync period, or any other time that the Hsync signal is
unavailable. The polarity of the COAST signal may be set
through the coast polarity register. Also, the polarity of the
Hsync signal may be set through the Hsync polarity
register. If not using automatic polarity detection, the
Hsync and COAST polarity bits should be set to match the
respective polarities of the input signals.
POWER MANAGEMENT
The AD9985 uses the activity detect circuits, the active interface
bits in the serial bus, the active interface override bits, and the
power-down bit to determine the correct power state. There are
three power states—full-power, seek mode, and power-down.
Table 8 summarizes how the AD9985 determines what power
mode to be in and which circuitry is powered on/off in each of
these modes. The power-down command has priority over the
automatic circuitry.
Table 8. Power-Down Mode Descriptions
Mode
Inputs
Power-Down1
Sync
Detect2
Powered On or
Comments
Full-
Power
1
Everything
Seek
Mode
1
0
Serial Bus, Sync
Activity Detect, SOG,
Band Gap Reference
Power-
Down
0
X
Serial Bus, Sync
Activity Detect, SOG,
Band Gap Reference
1Power-down is controlled via Bit 1 in serial bus Register 0FH.
2Sync detect is determined by OR’ing Bits 7, 4, and 1 in serial bus
Register 14H.
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