參數(shù)資料
型號(hào): ADA4000-1ARZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 3/16頁(yè)
文件大?。?/td> 0K
描述: IC OPAMP JFET 5MHZ PREC LP 8SOIC
產(chǎn)品培訓(xùn)模塊: Top Five Problems in Photodiode Opamp Circuits
設(shè)計(jì)資源: Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
標(biāo)準(zhǔn)包裝: 98
放大器類(lèi)型: J-FET
電路數(shù): 1
轉(zhuǎn)換速率: 20 V/µs
增益帶寬積: 5MHz
電流 - 輸入偏壓: 5pA
電壓 - 輸入偏移: 200µV
電流 - 電源: 1.35mA
電流 - 輸出 / 通道: 28mA
電壓 - 電源,單路/雙路(±): 8 V ~ 36 V,±4 V ~ 18 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
產(chǎn)品目錄頁(yè)面: 774 (CN2011-ZH PDF)
ADA4000-1/ADA4000-2/ADA4000-4
Rev. A | Page 11 of 16
)
SETTLING TIME
Settling time is the amount of time it takes the amplifier output
to reach and remain within a percentage of its final value. This
is an important parameter in data acquisition systems. Because
most bipolar DAC converters have current output, an external
op amp is required to convert the current to voltage. Therefore,
the amplifier settling time plays a role in the total settling time
of the output signal. A good approximation for the total settling
time is
() (
2
AMP
t
DAC
t
Total
t
S
+
=
The ADA4000-1/ADA4000-2/ADA4000-4 settle to within 0.1%
of their final value in less than 1.2 μs. The settling time has been
tested by using the configuration circuit in Figure 34.
The input signal is a 10 V pulse and the output is the error
signal for the settling time shown in Figure 33.
05
79
1-
0
35
200ns/DIV
200mV/DIV
5V/DIV
Figure 33. Settling Time Measurement Using the False Summing Node Method
ADA4000-1
V+
V–
+15V
–15V
10V p-p
05
79
1-
03
4
3
2
1
10k
AD828
V+
V–
+15V
–15V
20k
VOUT
1k
8
4
10k
V1
0
Figure 34. Settling Time Test Circuit
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